net: stmmac: dwmac-mediatek: fix wrong delay value issue when resume back

mac_delay value will be divided by 550/170 in mt2712_delay_ps2stage(),
which is invoked at the beginning of mt2712_set_delay(), and the value
should be restored at the end of mt2712_set_delay().
Or, mac_delay will be divided again when invoking mt2712_set_delay()
when resume back.
So, add mt2712_delay_stage2ps() to mt2712_set_delay() to recovery the
original mac_delay value.

Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index 79f2ee3..cea7a0c 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -130,6 +130,31 @@ static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
        }
 }
 
+static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
+{
+       struct mac_delay_struct *mac_delay = &plat->mac_delay;
+
+       switch (plat->phy_mode) {
+       case PHY_INTERFACE_MODE_MII:
+       case PHY_INTERFACE_MODE_RMII:
+               /* 550ps per stage for MII/RMII */
+               mac_delay->tx_delay *= 550;
+               mac_delay->rx_delay *= 550;
+               break;
+       case PHY_INTERFACE_MODE_RGMII:
+       case PHY_INTERFACE_MODE_RGMII_TXID:
+       case PHY_INTERFACE_MODE_RGMII_RXID:
+       case PHY_INTERFACE_MODE_RGMII_ID:
+               /* 170ps per stage for RGMII */
+               mac_delay->tx_delay *= 170;
+               mac_delay->rx_delay *= 170;
+               break;
+       default:
+               dev_err(plat->dev, "phy interface not supported\n");
+               break;
+       }
+}
+
 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
 {
        struct mac_delay_struct *mac_delay = &plat->mac_delay;
@@ -199,6 +224,8 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
        regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
        regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
 
+       mt2712_delay_stage2ps(plat);
+
        return 0;
 }