[arm] Remove +nofp from -mcpu=cortex-m55 options

Turns out for consistency with LLVM the +nofp option shouldn't remove ALL of FP and MVE, just the FP part of MVE.
This requires more surgery with feature bits so for GCC 10 I'd rather just not support +nofp for -mcpu=cortex-m55
and implement it properly for GCC 11.

2020-04-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
	* doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4c298b8..905d2b8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-28  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/arm-cpus.in (cortex-m55): Remove +nofp option.
+       * doc/invoke.texi (Arm Options): Remove -mcpu=cortex-m55 from +nofp option.
+
 2020-04-28  Matthew Malcomson  <matthew.malcomson@arm.com>
            Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 64b8ba7..728be50 100644 (file)
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1509,7 +1509,6 @@ begin cpu cortex-m55
  tune flags LDSCHED
  architecture armv8.1-m.main+mve.fp+fp.dp
  isa quirk_no_asmcpu
- option nofp remove ALL_FP MVE_FP
  costs v7m
  vendor 41
 end cpu cortex-m55

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 04b84e3..fed38e8 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -18841,7 +18841,7 @@ Disables the floating-point and SIMD instructions on
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
 @samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7},
 @samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35},
-@samp{cortex-a53},@samp{cortex-a55} and @samp{cortex-m55}.
+@samp{cortex-a53} and @samp{cortex-a55}.
 
 @item +nofp.dp
 Disables the double-precision component of the floating-point instructions