FSL DDR: Convert STXSSA to new DDR code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/stxssa/Makefile b/board/stxssa/Makefile
index e29cf95..9ab41ec 100644 (file)
--- a/board/stxssa/Makefile
+++ b/board/stxssa/Makefile
@@ -25,10 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).a
 
-COBJS  := $(BOARD).o law.o tlb.o
+COBJS-y        += $(BOARD).o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
 
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
 
 $(LIB):        $(obj).depend $(OBJS) $(SOBJS)

diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c
new file mode 100644 (file)
index 0000000..45372f4
--- /dev/null
+++ b/board/stxssa/ddr.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+       i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+       return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+                     unsigned int ctrl_num)
+{
+       unsigned int i;
+       unsigned int i2c_address = 0;
+
+       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+               if (ctrl_num == 0 && i == 0) {
+                       i2c_address = SPD_EEPROM_ADDRESS;
+               }
+               get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+       }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+       /*
+        * Factors to consider for CPO:
+        *      - frequency
+        *      - ddr1 vs. ddr2
+        */
+       popts->cpo_override = 0;
+
+       /*
+        * Factors to consider for write data delay:
+        *      - number of DIMMs
+        *
+        * 1 = 1/4 clock delay
+        * 2 = 1/2 clock delay
+        * 3 = 3/4 clock delay
+        * 4 = 1   clock delay
+        * 5 = 5/4 clock delay
+        * 6 = 3/2 clock delay
+        */
+       popts->write_data_delay = 3;
+
+       /*
+        * Factors to consider for half-strength driver enable:
+        *      - number of DIMMs installed
+        */
+       popts->half_strength_driver_enable = 0;
+}

diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 2c4b546..124e123 100644 (file)
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -32,7 +32,9 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
@@ -308,7 +310,9 @@ initdram (int board_type)
        }
 #endif
 
-       dram_size = spd_sdram ();
+       dram_size = fsl_ddr_sdram();
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC)
        /* Initialize and enable DDR ECC.

diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds
index b0a9d68..93bedda 100644 (file)
--- a/board/stxssa/u-boot.lds
+++ b/board/stxssa/u-boot.lds
@@ -76,7 +76,6 @@ SECTIONS
     cpu/mpc85xx/cpu_init.o (.text)
     cpu/mpc85xx/cpu.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/spd_sdram.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)

diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h
index 4f1c156..ac349df 100644 (file)
--- a/include/configs/stxssa.h
+++ b/include/configs/stxssa.h
@@ -47,10 +47,6 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support*/
 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
-#undef CONFIG_DDR_DLL                  /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
@@ -131,19 +127,27 @@
 #define CFG_CCSRBAR_PHYS       CFG_CCSRBAR     /* physical addr of CCSRBAR */
 #define CFG_IMMR               CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 
+/* DDR Setup */
+#define CONFIG_FSL_DDR1
+#define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
 
-/*
- * DDR Setup
- */
+#undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
+#undef CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
 
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory  */
+#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory*/
 #define CFG_SDRAM_BASE         CFG_DDR_SDRAM_BASE
 
-#define SPD_EEPROM_ADDRESS     0x54            /*  DDR DIMM */
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS     0x54    /* CTLR 0 DIMM 0 */
 
 #undef CONFIG_CLOCKS_IN_MHZ