class Argument;
class BasicBlock;
class BranchProbabilityInfo;
+class LegacyDivergenceAnalysis;
class Function;
class Instruction;
class MachineFunction;
class SelectionDAG;
class TargetLowering;
-template <typename T> class GenericSSAContext;
-using SSAContext = GenericSSAContext<Function>;
-template <typename T> class GenericUniformityInfo;
-using UniformityInfo = GenericUniformityInfo<SSAContext>;
-
//===--------------------------------------------------------------------===//
/// FunctionLoweringInfo - This contains information that is global to a
/// function that is used when lowering a region of the function.
const TargetLowering *TLI;
MachineRegisterInfo *RegInfo;
BranchProbabilityInfo *BPI;
- const UniformityInfo *UA;
+ const LegacyDivergenceAnalysis *DA;
/// CanLowerReturn - true iff the function's return value can be lowered to
/// registers.
bool CanLowerReturn;
class FunctionVarLocs;
class GlobalValue;
struct KnownBits;
+class LegacyDivergenceAnalysis;
class LLVMContext;
class MachineBasicBlock;
class MachineConstantPoolValue;
class TargetSubtargetInfo;
class Value;
-template <typename T> class GenericSSAContext;
-using SSAContext = GenericSSAContext<Function>;
-template <typename T> class GenericUniformityInfo;
-using UniformityInfo = GenericUniformityInfo<SSAContext>;
-
class SDVTListNode : public FoldingSetNode {
friend struct FoldingSetTrait<SDVTListNode>;
LLVMContext *Context;
CodeGenOpt::Level OptLevel;
- UniformityInfo *UA = nullptr;
+ LegacyDivergenceAnalysis * DA = nullptr;
FunctionLoweringInfo * FLI = nullptr;
/// The function-level optimization remark emitter. Used to emit remarks
/// Prepare this SelectionDAG to process code in the given MachineFunction.
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
- UniformityInfo *UA, ProfileSummaryInfo *PSIin,
+ LegacyDivergenceAnalysis *Divergence, ProfileSummaryInfo *PSIin,
BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs);
void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
const TargetLibraryInfo &getLibInfo() const { return *LibInfo; }
const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }
- const UniformityInfo *getUniformityInfo() const { return UA; }
+ const LegacyDivergenceAnalysis *getDivergenceAnalysis() const { return DA; }
/// Returns the result of the AssignmentTrackingAnalysis pass if it's
/// available, otherwise return nullptr.
const FunctionVarLocs *getFunctionVarLocs() const { return FnVarLocs; }
class IntrinsicInst;
class IRBuilderBase;
struct KnownBits;
+class LegacyDivergenceAnalysis;
class LLVMContext;
class MachineBasicBlock;
class MachineFunction;
virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
FunctionLoweringInfo *FLI,
- UniformityInfo *UA) const {
+ LegacyDivergenceAnalysis *DA) const {
return false;
}
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/ADT/APInt.h"
-#include "llvm/Analysis/UniformityAnalysis.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
TLI = MF->getSubtarget().getTargetLowering();
RegInfo = &MF->getRegInfo();
const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
- UA = DAG->getUniformityInfo();
+ DA = DAG->getDivergenceAnalysis();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
}
Register FunctionLoweringInfo::CreateRegs(const Value *V) {
- return CreateRegs(V->getType(), UA && UA->isDivergent(V) &&
- !TLI->requiresUniformRegister(*MF, V));
+ return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
+ !TLI->requiresUniformRegister(*MF, V));
}
/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
void SelectionDAG::init(MachineFunction &NewMF,
OptimizationRemarkEmitter &NewORE, Pass *PassPtr,
const TargetLibraryInfo *LibraryInfo,
- UniformityInfo *NewUA, ProfileSummaryInfo *PSIin,
- BlockFrequencyInfo *BFIin,
+ LegacyDivergenceAnalysis *Divergence,
+ ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin,
FunctionVarLocs const *VarLocs) {
MF = &NewMF;
SDAGISelPass = PassPtr;
TSI = getSubtarget().getSelectionDAGInfo();
LibInfo = LibraryInfo;
Context = &MF->getFunction().getContext();
- UA = NewUA;
+ DA = Divergence;
PSI = PSIin;
BFI = BFIin;
FnVarLocs = VarLocs;
return SDValue(E, 0);
auto *N = newSDNode<RegisterSDNode>(RegNo, VT);
- N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(N, FLI, UA);
+ N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(N, FLI, DA);
CSEMap.InsertNode(N, IP);
InsertNode(N);
return SDValue(N, 0);
bool SelectionDAG::calculateDivergence(SDNode *N) {
if (TLI->isSDNodeAlwaysUniform(N)) {
- assert(!TLI->isSDNodeSourceOfDivergence(N, FLI, UA) &&
+ assert(!TLI->isSDNodeSourceOfDivergence(N, FLI, DA) &&
"Conflicting divergence information!");
return false;
}
- if (TLI->isSDNodeSourceOfDivergence(N, FLI, UA))
+ if (TLI->isSDNodeSourceOfDivergence(N, FLI, DA))
return true;
for (const auto &Op : N->ops()) {
if (Op.Val.getValueType() != MVT::Other && Op.getNode()->isDivergent())
Node->NumOperands = Vals.size();
Node->OperandList = Ops;
if (!TLI->isSDNodeAlwaysUniform(Node)) {
- IsDivergent |= TLI->isSDNodeSourceOfDivergence(Node, FLI, UA);
+ IsDivergent |= TLI->isSDNodeSourceOfDivergence(Node, FLI, DA);
Node->SDNodeBits.IsDivergent = IsDivergent;
}
checkForCycles(Node);
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/Analysis/CFG.h"
#include "llvm/Analysis/LazyBlockFrequencyInfo.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/Analysis/UniformityAnalysis.h"
#include "llvm/CodeGen/AssignmentTrackingAnalysis.h"
#include "llvm/CodeGen/CodeGenCommonISel.h"
#include "llvm/CodeGen/FastISel.h"
LLVM_DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
- UniformityInfo *UA = nullptr;
- if (auto *UAPass = getAnalysisIfAvailable<UniformityInfoWrapperPass>())
- UA = &UAPass->getUniformityInfo();
- CurDAG->init(*MF, *ORE, this, LibInfo, UA, PSI, BFI, FnVarLocs);
+ CurDAG->init(*MF, *ORE, this, LibInfo,
+ getAnalysisIfAvailable<LegacyDivergenceAnalysis>(), PSI, BFI,
+ FnVarLocs);
FuncInfo->set(Fn, *MF, CurDAG);
SwiftError->setFunction(*MF);
#include "MCTargetDesc/R600MCTargetDesc.h"
#include "R600RegisterInfo.h"
#include "SIMachineFunctionInfo.h"
-#include "llvm/Analysis/UniformityAnalysis.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
"AMDGPU DAG->DAG Pattern Instruction Selection", false, false)
INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)
INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis)
-INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)
#ifdef EXPENSIVE_CHECKS
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
void AMDGPUDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<AMDGPUArgumentUsageInfo>();
- AU.addRequired<UniformityInfoWrapperPass>();
+ AU.addRequired<LegacyDivergenceAnalysis>();
#ifdef EXPENSIVE_CHECKS
AU.addRequired<DominatorTreeWrapperPass>();
AU.addRequired<LoopInfoWrapperPass>();
#include "SIRegisterInfo.h"
#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
-#include "llvm/Analysis/UniformityAnalysis.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/KnownBits.h"
#include "llvm/Support/ModRef.h"
+#include "llvm/Support/KnownBits.h"
using namespace llvm;
return false;
}
-bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode *N,
- FunctionLoweringInfo *FLI,
- UniformityInfo *UA) const {
+bool SITargetLowering::isSDNodeSourceOfDivergence(
+ const SDNode *N, FunctionLoweringInfo *FLI,
+ LegacyDivergenceAnalysis *KDA) const {
switch (N->getOpcode()) {
case ISD::CopyFromReg: {
const RegisterSDNode *R = cast<RegisterSDNode>(N->getOperand(1));
return !TRI->isSGPRReg(MRI, Reg);
if (const Value *V = FLI->getValueFromVirtualReg(R->getReg()))
- return UA->isDivergent(V);
+ return KDA->isDivergent(V);
assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N));
return !TRI->isSGPRReg(MRI, Reg);
// uniform values (as produced by the mask results of control flow intrinsics)
// used outside of divergent blocks. The phi users need to also be treated as
// always uniform.
-//
-// FIXME: DA is no longer in-use. Does this still apply to UniformityAnalysis?
static bool hasCFUser(const Value *V, SmallPtrSet<const Value *, 16> &Visited,
unsigned WaveSize) {
// FIXME: We assume we never cast the mask results of a control flow
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R,
const MachineRegisterInfo &MRI,
unsigned Depth = 0) const override;
- bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
- UniformityInfo *UA) const override;
+ bool isSDNodeSourceOfDivergence(const SDNode *N,
+ FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
bool hasMemSDNodeUser(SDNode *N) const;
; GCN-O0-NEXT: Safe Stack instrumentation pass
; GCN-O0-NEXT: Insert stack protectors
; GCN-O0-NEXT: Dominator Tree Construction
-; GCN-O0-NEXT: Cycle Info Analysis
-; GCN-O0-NEXT: Uniformity Analysis
+; GCN-O0-NEXT: Post-Dominator Tree Construction
+; GCN-O0-NEXT: Natural Loop Information
+; GCN-O0-NEXT: Legacy Divergence Analysis
; GCN-O0-NEXT: Assignment Tracking Analysis
; GCN-O0-NEXT: AMDGPU DAG->DAG Pattern Instruction Selection
; GCN-O0-NEXT: MachineDominator Tree Construction
; GCN-O1-NEXT: Safe Stack instrumentation pass
; GCN-O1-NEXT: Insert stack protectors
; GCN-O1-NEXT: Dominator Tree Construction
-; GCN-O1-NEXT: Cycle Info Analysis
-; GCN-O1-NEXT: Uniformity Analysis
+; GCN-O1-NEXT: Post-Dominator Tree Construction
+; GCN-O1-NEXT: Natural Loop Information
+; GCN-O1-NEXT: Legacy Divergence Analysis
; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O1-NEXT: Function Alias Analysis Results
-; GCN-O1-NEXT: Natural Loop Information
-; GCN-O1-NEXT: Post-Dominator Tree Construction
; GCN-O1-NEXT: Branch Probability Analysis
; GCN-O1-NEXT: Assignment Tracking Analysis
; GCN-O1-NEXT: Lazy Branch Probability Analysis
; GCN-O1-OPTS-NEXT: Safe Stack instrumentation pass
; GCN-O1-OPTS-NEXT: Insert stack protectors
; GCN-O1-OPTS-NEXT: Dominator Tree Construction
-; GCN-O1-OPTS-NEXT: Cycle Info Analysis
-; GCN-O1-OPTS-NEXT: Uniformity Analysis
+; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
+; GCN-O1-OPTS-NEXT: Natural Loop Information
+; GCN-O1-OPTS-NEXT: Legacy Divergence Analysis
; GCN-O1-OPTS-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O1-OPTS-NEXT: Function Alias Analysis Results
-; GCN-O1-OPTS-NEXT: Natural Loop Information
-; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
; GCN-O1-OPTS-NEXT: Branch Probability Analysis
; GCN-O1-OPTS-NEXT: Assignment Tracking Analysis
; GCN-O1-OPTS-NEXT: Lazy Branch Probability Analysis
; GCN-O2-NEXT: Safe Stack instrumentation pass
; GCN-O2-NEXT: Insert stack protectors
; GCN-O2-NEXT: Dominator Tree Construction
-; GCN-O2-NEXT: Cycle Info Analysis
-; GCN-O2-NEXT: Uniformity Analysis
+; GCN-O2-NEXT: Post-Dominator Tree Construction
+; GCN-O2-NEXT: Natural Loop Information
+; GCN-O2-NEXT: Legacy Divergence Analysis
; GCN-O2-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O2-NEXT: Function Alias Analysis Results
-; GCN-O2-NEXT: Natural Loop Information
-; GCN-O2-NEXT: Post-Dominator Tree Construction
; GCN-O2-NEXT: Branch Probability Analysis
; GCN-O2-NEXT: Assignment Tracking Analysis
; GCN-O2-NEXT: Lazy Branch Probability Analysis
; GCN-O3-NEXT: Safe Stack instrumentation pass
; GCN-O3-NEXT: Insert stack protectors
; GCN-O3-NEXT: Dominator Tree Construction
-; GCN-O3-NEXT: Cycle Info Analysis
-; GCN-O3-NEXT: Uniformity Analysis
+; GCN-O3-NEXT: Post-Dominator Tree Construction
+; GCN-O3-NEXT: Natural Loop Information
+; GCN-O3-NEXT: Legacy Divergence Analysis
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O3-NEXT: Function Alias Analysis Results
-; GCN-O3-NEXT: Natural Loop Information
-; GCN-O3-NEXT: Post-Dominator Tree Construction
; GCN-O3-NEXT: Branch Probability Analysis
; GCN-O3-NEXT: Assignment Tracking Analysis
; GCN-O3-NEXT: Lazy Branch Probability Analysis
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