default:
break;
}
+ break;
}
default:
}
}
// else fallthrough
+ LLVM_FALLTHROUGH;
// The MC library also has a right-shift operator, but it isn't consistently
// signed or unsigned between different targets.
case ISD::SETLT:
case ISD::SETLE:
std::swap(TrueOpnd, FalseOpnd);
- // Fall through
+ LLVM_FALLTHROUGH;
case ISD::SETOGT:
case ISD::SETUGT:
case ISD::SETOGE:
if (!ResourcesModel->canReserveResources(&TII->get(
SU->getNode()->getMachineOpcode())))
return false;
+ break;
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
!FormValue.isFormClass(DWARFFormValue::FC_Flag)) ||
FormValue.getForm() == dwarf::DW_FORM_sdata)
return false;
+ break;
default:
break;
}
//===----------------------------------------------------------------------===//
#include "llvm/Demangle/Demangle.h"
+#include "llvm/Support/Compiler.h"
// This file exports a single function: llvm::itanium_demangle.
// It also has no dependencies on the rest of llvm. It is implemented this way
break;
}
}
- // falls through
+ LLVM_FALLTHROUGH;
default:
// must check for builtin-types before class-enum-types to avoid
// ambiguities with operator-names
}
}
}
+ break;
}
default:
break;
default:
break;
}
+ break;
case ELF::EM_BPF:
switch (Type) {
#include "llvm/BinaryFormat/ELFRelocs/BPF.def"
case ARM::ArchKind::ARMV8_2A:
case ARM::ArchKind::ARMV8_3A:
return ARM::ProfileKind::A;
- LLVM_FALLTHROUGH;
case ARM::ArchKind::ARMV2:
case ARM::ArchKind::ARMV2A:
case ARM::ArchKind::ARMV3:
return selectAtomicCmpXchg(cast<AtomicCmpXchgInst>(I));
}
- // fall-back to target-independent instruction selection.
- return selectOperator(I, I->getOpcode());
// Silence warnings.
(void)&CC_AArch64_DarwinPCS_VarArg;
(void)&CC_AArch64_Win64_VarArg;
+
+ // fall-back to target-independent instruction selection.
+ return selectOperator(I, I->getOpcode());
}
namespace llvm {
case MVT::i8:
case MVT::i16:
needsExt = true;
- // Intentional fall-through.
+ LLVM_FALLTHROUGH;
case MVT::i32:
if (isThumb2) {
if (!UseImm)
case AtomicOrdering::SequentiallyConsistent:
if (!Inst->hasAtomicStore())
return nullptr; // Nothing to do
- /*FALLTHROUGH*/
+ LLVM_FALLTHROUGH;
case AtomicOrdering::Release:
case AtomicOrdering::AcquireRelease:
if (Subtarget->preferISHSTBarriers())
case ARM::VLD4q32_UPD:
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
return MCDisassembler::Fail;
+ break;
default:
break;
}
case ARM::t2STRs:
if (Rn == 15)
return MCDisassembler::Fail;
+ break;
default:
break;
}
break;
case ARM::t2LDRSBs:
Inst.setOpcode(ARM::t2PLIs);
+ break;
default:
break;
}
case ARM::t2STRHi12:
if (Rn == 15)
return MCDisassembler::Fail;
+ break;
default:
break;
}
case Instruction::GetElementPtr:
if (cast<GetElementPtrInst>(I)->hasAllZeroIndices())
continue;
+ break;
default:
break;
}
Constant *Bit = importConstant(Slot, CSByConstantArg.first, "bit", Int8Ty,
ResByArg.Bit);
applyVirtualConstProp(CSByConstantArg.second, "", Byte, Bit);
+ break;
}
default:
break;
// seed additional demotion, we save the truncated value.
case Instruction::Trunc:
Roots.push_back(I->getOperand(0));
+ break;
case Instruction::ZExt:
case Instruction::SExt:
break;
if (addComma)
OS << ",";
OS << "Attribute::InaccessibleMemOrArgMemOnly";
+ break;
case CodeGenIntrinsic::ReadWriteMem:
break;
}