drm/amdgpu: add PSP driver for vega10 (v2)
authorHuang Rui <ray.huang@amd.com>
Fri, 3 Mar 2017 23:37:23 +0000 (18:37 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 03:54:48 +0000 (23:54 -0400)
PSP is responsible for firmware loading on SOC-15 asics.

v2: fix memory leak (Ken)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/Makefile
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c [new file with mode: 0644]
drivers/gpu/drm/amd/amdgpu/psp_v3_1.h [new file with mode: 0644]
drivers/gpu/drm/amd/include/amd_shared.h

index cab8eec..48a9c03 100644 (file)
@@ -51,6 +51,11 @@ amdgpu-y += \
        cz_ih.o \
        vega10_ih.o
 
+# add PSP block
+amdgpu-y += \
+       amdgpu_psp.o \
+       psp_v3_1.o
+
 # add SMC block
 amdgpu-y += \
        amdgpu_dpm.o \
index 2339046..c571f68 100644 (file)
@@ -52,6 +52,7 @@
 #include "amdgpu_irq.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_ttm.h"
+#include "amdgpu_psp.h"
 #include "amdgpu_gds.h"
 #include "amdgpu_sync.h"
 #include "amdgpu_ring.h"
@@ -1213,6 +1214,10 @@ struct amdgpu_firmware {
        struct amdgpu_bo *fw_buf;
        unsigned int fw_size;
        unsigned int max_ucodes;
+       /* firmwares are loaded by psp instead of smu from vega10 */
+       const struct amdgpu_psp_funcs *funcs;
+       struct amdgpu_bo *rbuf;
+       struct mutex mutex;
 };
 
 /*
@@ -1571,6 +1576,9 @@ struct amdgpu_device {
        /* firmwares */
        struct amdgpu_firmware          firmware;
 
+       /* PSP */
+       struct psp_context              psp;
+
        /* GDS */
        struct amdgpu_gds               gds;
 
@@ -1825,6 +1833,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
+#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 
 /* Common functions */
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
index dd9f493..cf45fb9 100644 (file)
@@ -1837,6 +1837,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         * can recall function without having locking issues */
        mutex_init(&adev->vm_manager.lock);
        atomic_set(&adev->irq.ih.lock, 0);
+       mutex_init(&adev->firmware.mutex);
        mutex_init(&adev->pm.mutex);
        mutex_init(&adev->gfx.gpu_clock_mutex);
        mutex_init(&adev->srbm_mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
new file mode 100644 (file)
index 0000000..4731015
--- /dev/null
@@ -0,0 +1,481 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+
+#include <linux/firmware.h>
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+#include "psp_v3_1.h"
+
+static void psp_set_funcs(struct amdgpu_device *adev);
+
+static int psp_early_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       psp_set_funcs(adev);
+
+       return 0;
+}
+
+static int psp_sw_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct psp_context *psp = &adev->psp;
+       int ret;
+
+       switch (adev->asic_type) {
+       case CHIP_VEGA10:
+               psp->init_microcode = psp_v3_1_init_microcode;
+               psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
+               psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
+               psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
+               psp->ring_init = psp_v3_1_ring_init;
+               psp->cmd_submit = psp_v3_1_cmd_submit;
+               psp->compare_sram_data = psp_v3_1_compare_sram_data;
+               psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       psp->adev = adev;
+
+       ret = psp_init_microcode(psp);
+       if (ret) {
+               DRM_ERROR("Failed to load psp firmware!\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+static int psp_sw_fini(void *handle)
+{
+       return 0;
+}
+
+int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
+                uint32_t reg_val, uint32_t mask, bool check_changed)
+{
+       uint32_t val;
+       int i;
+       struct amdgpu_device *adev = psp->adev;
+
+       val = RREG32(reg_index);
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               if (check_changed) {
+                       if (val != reg_val)
+                               return 0;
+               } else {
+                       if ((val & mask) == reg_val)
+                               return 0;
+               }
+               udelay(1);
+       }
+
+       return -ETIME;
+}
+
+static int
+psp_cmd_submit_buf(struct psp_context *psp,
+                  struct amdgpu_firmware_info *ucode,
+                  struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
+                  int index)
+{
+       int ret;
+       struct amdgpu_bo *cmd_buf_bo;
+       uint64_t cmd_buf_mc_addr;
+       struct psp_gfx_cmd_resp *cmd_buf_mem;
+       struct amdgpu_device *adev = psp->adev;
+
+       ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &cmd_buf_bo, &cmd_buf_mc_addr,
+                                     (void **)&cmd_buf_mem);
+       if (ret)
+               return ret;
+
+       memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
+
+       memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
+
+       ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
+                            fence_mc_addr, index);
+
+       while (*((unsigned int *)psp->fence_buf) != index) {
+               msleep(1);
+       };
+
+       amdgpu_bo_free_kernel(&cmd_buf_bo,
+                             &cmd_buf_mc_addr,
+                             (void **)&cmd_buf_mem);
+
+       return ret;
+}
+
+static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+                                uint64_t tmr_mc, uint32_t size)
+{
+       cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
+       cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
+       cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
+       cmd->cmd.cmd_setup_tmr.buf_size = size;
+}
+
+/* Set up Trusted Memory Region */
+static int psp_tmr_init(struct psp_context *psp)
+{
+       int ret;
+       struct psp_gfx_cmd_resp *cmd;
+
+       cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+       if (!cmd)
+               return -ENOMEM;
+
+       /*
+        * Allocate 3M memory aligned to 1M from Frame Buffer (local
+        * physical).
+        *
+        * Note: this memory need be reserved till the driver
+        * uninitializes.
+        */
+       ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+       if (ret)
+               goto failed;
+
+       psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
+
+       ret = psp_cmd_submit_buf(psp, NULL, cmd,
+                                psp->fence_buf_mc_addr, 1);
+       if (ret)
+               goto failed_mem;
+
+       kfree(cmd);
+
+       return 0;
+
+failed_mem:
+       amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+failed:
+       kfree(cmd);
+       return ret;
+}
+
+static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+                                uint64_t asd_mc, uint64_t asd_mc_shared,
+                                uint32_t size, uint32_t shared_size)
+{
+       cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
+       cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
+       cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
+       cmd->cmd.cmd_load_ta.app_len = size;
+
+       cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
+       cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
+       cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
+}
+
+static int psp_asd_load(struct psp_context *psp)
+{
+       int ret;
+       struct amdgpu_bo *asd_bo, *asd_shared_bo;
+       uint64_t asd_mc_addr, asd_shared_mc_addr;
+       void *asd_buf, *asd_shared_buf;
+       struct psp_gfx_cmd_resp *cmd;
+
+       cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+       if (!cmd)
+               return -ENOMEM;
+
+       /*
+        * Allocate 16k memory aligned to 4k from Frame Buffer (local
+        * physical) for shared ASD <-> Driver
+        */
+       ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &asd_shared_bo, &asd_shared_mc_addr, &asd_buf);
+       if (ret)
+               goto failed;
+
+       /*
+        * Allocate 256k memory aligned to 4k from Frame Buffer (local
+        * physical) for ASD firmware
+        */
+       ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_BIN_SIZE, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &asd_bo, &asd_mc_addr, &asd_buf);
+       if (ret)
+               goto failed_mem;
+
+       memcpy(asd_buf, psp->asd_start_addr, psp->asd_ucode_size);
+
+       psp_prep_asd_cmd_buf(cmd, asd_mc_addr, asd_shared_mc_addr,
+                            psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
+
+       ret = psp_cmd_submit_buf(psp, NULL, cmd,
+                                psp->fence_buf_mc_addr, 2);
+       if (ret)
+               goto failed_mem1;
+
+       amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf);
+       amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
+       kfree(cmd);
+
+       return 0;
+
+failed_mem1:
+       amdgpu_bo_free_kernel(&asd_bo, &asd_mc_addr, &asd_buf);
+failed_mem:
+       amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
+failed:
+       kfree(cmd);
+       return ret;
+}
+
+static int psp_load_fw(struct amdgpu_device *adev)
+{
+       int ret;
+       struct psp_gfx_cmd_resp *cmd;
+       int i;
+       struct amdgpu_firmware_info *ucode;
+       struct psp_context *psp = &adev->psp;
+
+       cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+       if (!cmd)
+               return -ENOMEM;
+
+       ret = psp_bootloader_load_sysdrv(psp);
+       if (ret)
+               goto failed;
+
+       ret = psp_bootloader_load_sos(psp);
+       if (ret)
+               goto failed;
+
+       ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
+       if (ret)
+               goto failed;
+
+       ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &psp->fence_buf_bo,
+                                     &psp->fence_buf_mc_addr,
+                                     &psp->fence_buf);
+       if (ret)
+               goto failed;
+
+       memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
+
+       ret = psp_tmr_init(psp);
+       if (ret)
+               goto failed_mem;
+
+       ret = psp_asd_load(psp);
+       if (ret)
+               goto failed_mem;
+
+       for (i = 0; i < adev->firmware.max_ucodes; i++) {
+               ucode = &adev->firmware.ucode[i];
+               if (!ucode->fw)
+                       continue;
+
+               if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
+                   psp_smu_reload_quirk(psp))
+                       continue;
+
+               ret = psp_prep_cmd_buf(ucode, cmd);
+               if (ret)
+                       goto failed_mem;
+
+               ret = psp_cmd_submit_buf(psp, ucode, cmd,
+                                        psp->fence_buf_mc_addr, i + 3);
+               if (ret)
+                       goto failed_mem;
+
+#if 0
+               /* check if firmware loaded sucessfully */
+               if (!amdgpu_psp_check_fw_loading_status(adev, i))
+                       return -EINVAL;
+#endif
+       }
+
+       amdgpu_bo_free_kernel(&psp->fence_buf_bo,
+                             &psp->fence_buf_mc_addr, &psp->fence_buf);
+       kfree(cmd);
+
+       return 0;
+
+failed_mem:
+       amdgpu_bo_free_kernel(&psp->fence_buf_bo,
+                             &psp->fence_buf_mc_addr, &psp->fence_buf);
+failed:
+       kfree(cmd);
+       return ret;
+}
+
+static int psp_hw_init(void *handle)
+{
+       int ret;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+               return 0;
+
+       mutex_lock(&adev->firmware.mutex);
+       /*
+        * This sequence is just used on hw_init only once, no need on
+        * resume.
+        */
+       ret = amdgpu_ucode_init_bo(adev);
+       if (ret)
+               goto failed;
+
+       ret = psp_load_fw(adev);
+       if (ret) {
+               DRM_ERROR("PSP firmware loading failed\n");
+               goto failed;
+       }
+
+       mutex_unlock(&adev->firmware.mutex);
+       return 0;
+
+failed:
+       adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
+       mutex_unlock(&adev->firmware.mutex);
+       return -EINVAL;
+}
+
+static int psp_hw_fini(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct psp_context *psp = &adev->psp;
+
+       if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+               amdgpu_ucode_fini_bo(adev);
+
+       if (psp->tmr_buf)
+               amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+
+       return 0;
+}
+
+static int psp_suspend(void *handle)
+{
+       return 0;
+}
+
+static int psp_resume(void *handle)
+{
+       int ret;
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
+               return 0;
+
+       mutex_lock(&adev->firmware.mutex);
+
+       ret = psp_load_fw(adev);
+       if (ret)
+               DRM_ERROR("PSP resume failed\n");
+
+       mutex_unlock(&adev->firmware.mutex);
+
+       return ret;
+}
+
+static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
+                                       enum AMDGPU_UCODE_ID ucode_type)
+{
+       struct amdgpu_firmware_info *ucode = NULL;
+
+       if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+               DRM_INFO("firmware is not loaded by PSP\n");
+               return true;
+       }
+
+       if (!adev->firmware.fw_size)
+               return false;
+
+       ucode = &adev->firmware.ucode[ucode_type];
+       if (!ucode->fw || !ucode->ucode_size)
+               return false;
+
+       return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
+}
+
+static int psp_set_clockgating_state(void *handle,
+                                    enum amd_clockgating_state state)
+{
+       return 0;
+}
+
+static int psp_set_powergating_state(void *handle,
+                                    enum amd_powergating_state state)
+{
+       return 0;
+}
+
+const struct amd_ip_funcs psp_ip_funcs = {
+       .name = "psp",
+       .early_init = psp_early_init,
+       .late_init = NULL,
+       .sw_init = psp_sw_init,
+       .sw_fini = psp_sw_fini,
+       .hw_init = psp_hw_init,
+       .hw_fini = psp_hw_fini,
+       .suspend = psp_suspend,
+       .resume = psp_resume,
+       .is_idle = NULL,
+       .wait_for_idle = NULL,
+       .soft_reset = NULL,
+       .set_clockgating_state = psp_set_clockgating_state,
+       .set_powergating_state = psp_set_powergating_state,
+};
+
+static const struct amdgpu_psp_funcs psp_funcs = {
+       .check_fw_loading_status = psp_check_fw_loading_status,
+};
+
+static void psp_set_funcs(struct amdgpu_device *adev)
+{
+       if (NULL == adev->firmware.funcs)
+               adev->firmware.funcs = &psp_funcs;
+}
+
+const struct amdgpu_ip_block_version psp_v3_1_ip_block =
+{
+       .type = AMD_IP_BLOCK_TYPE_PSP,
+       .major = 3,
+       .minor = 1,
+       .rev = 0,
+       .funcs = &psp_ip_funcs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
new file mode 100644 (file)
index 0000000..e9f35e0
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+#ifndef __AMDGPU_PSP_H__
+#define __AMDGPU_PSP_H__
+
+#include "amdgpu.h"
+#include "psp_gfx_if.h"
+
+#define PSP_FENCE_BUFFER_SIZE  0x1000
+#define PSP_CMD_BUFFER_SIZE    0x1000
+#define PSP_ASD_BIN_SIZE       0x40000
+#define PSP_ASD_SHARED_MEM_SIZE        0x4000
+
+enum psp_ring_type
+{
+       PSP_RING_TYPE__INVALID = 0,
+       /*
+        * These values map to the way the PSP kernel identifies the
+        * rings.
+        */
+       PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
+       PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
+};
+
+struct psp_ring
+{
+       enum psp_ring_type              ring_type;
+       struct psp_gfx_rb_frame         *ring_mem;
+       uint64_t                        ring_mem_mc_addr;
+       void                            *ring_mem_handle;
+       uint32_t                        ring_size;
+};
+
+struct psp_context
+{
+       struct amdgpu_device            *adev;
+       struct psp_ring                 km_ring;
+
+       int (*init_microcode)(struct psp_context *psp);
+       int (*bootloader_load_sysdrv)(struct psp_context *psp);
+       int (*bootloader_load_sos)(struct psp_context *psp);
+       int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
+                           struct psp_gfx_cmd_resp *cmd);
+       int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
+       int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
+                         uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
+       bool (*compare_sram_data)(struct psp_context *psp,
+                                 struct amdgpu_firmware_info *ucode,
+                                 enum AMDGPU_UCODE_ID ucode_type);
+       bool (*smu_reload_quirk)(struct psp_context *psp);
+
+       /* sos firmware */
+       const struct firmware           *sos_fw;
+       uint32_t                        sos_fw_version;
+       uint32_t                        sos_feature_version;
+       uint32_t                        sys_bin_size;
+       uint32_t                        sos_bin_size;
+       uint8_t                         *sys_start_addr;
+       uint8_t                         *sos_start_addr;
+
+       /* tmr buffer */
+       struct amdgpu_bo                *tmr_bo;
+       uint64_t                        tmr_mc_addr;
+       void                            *tmr_buf;
+
+       /* asd firmware */
+       const struct firmware           *asd_fw;
+       uint32_t                        asd_fw_version;
+       uint32_t                        asd_feature_version;
+       uint32_t                        asd_ucode_size;
+       uint8_t                         *asd_start_addr;
+
+       /* fence buffer */
+       struct amdgpu_bo                *fence_buf_bo;
+       uint64_t                        fence_buf_mc_addr;
+       void                            *fence_buf;
+};
+
+struct amdgpu_psp_funcs {
+       bool (*check_fw_loading_status)(struct amdgpu_device *adev,
+                                       enum AMDGPU_UCODE_ID);
+};
+
+#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
+#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
+#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
+               (psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
+#define psp_compare_sram_data(psp, ucode, type) \
+               (psp)->compare_sram_data((psp), (ucode), (type))
+#define psp_init_microcode(psp) \
+               ((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
+#define psp_bootloader_load_sysdrv(psp) \
+               ((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0)
+#define psp_bootloader_load_sos(psp) \
+               ((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
+#define psp_smu_reload_quirk(psp) \
+               ((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
+
+extern const struct amd_ip_funcs psp_ip_funcs;
+
+extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
+extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
+                       uint32_t field_val, uint32_t mask, bool check_changed);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
new file mode 100644 (file)
index 0000000..8da6da9
--- /dev/null
@@ -0,0 +1,269 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _PSP_TEE_GFX_IF_H_
+#define _PSP_TEE_GFX_IF_H_
+
+#define PSP_GFX_CMD_BUF_VERSION     0x00000001
+
+#define GFX_CMD_STATUS_MASK         0x0000FFFF
+#define GFX_CMD_ID_MASK             0x000F0000
+#define GFX_CMD_RESERVED_MASK       0x7FF00000
+#define GFX_CMD_RESPONSE_MASK       0x80000000
+
+/* TEE Gfx Command IDs for the register interface.
+*  Command ID must be between 0x00010000 and 0x000F0000.
+*/
+enum psp_gfx_crtl_cmd_id
+{
+    GFX_CTRL_CMD_ID_INIT_RBI_RING   = 0x00010000,   /* initialize RBI ring */
+    GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000,   /* initialize GPCOM ring */
+    GFX_CTRL_CMD_ID_DESTROY_RINGS   = 0x00030000,   /* destroy rings */
+    GFX_CTRL_CMD_ID_CAN_INIT_RINGS  = 0x00040000,   /* is it allowed to initialized the rings */
+
+    GFX_CTRL_CMD_ID_MAX             = 0x000F0000,   /* max command ID */
+};
+
+
+/* Control registers of the TEE Gfx interface. These are located in
+*  SRBM-to-PSP mailbox registers (total 8 registers).
+*/
+struct psp_gfx_ctrl
+{
+    volatile uint32_t   cmd_resp;         /* +0   Command/Response register for Gfx commands */
+    volatile uint32_t   rbi_wptr;         /* +4   Write pointer (index) of RBI ring */
+    volatile uint32_t   rbi_rptr;         /* +8   Read pointer (index) of RBI ring */
+    volatile uint32_t   gpcom_wptr;       /* +12  Write pointer (index) of GPCOM ring */
+    volatile uint32_t   gpcom_rptr;       /* +16  Read pointer (index) of GPCOM ring */
+    volatile uint32_t   ring_addr_lo;     /* +20  bits [31:0] of physical address of ring buffer */
+    volatile uint32_t   ring_addr_hi;     /* +24  bits [63:32] of physical address of ring buffer */
+    volatile uint32_t   ring_buf_size;    /* +28  Ring buffer size (in bytes) */
+
+};
+
+
+/* Response flag is set in the command when command is completed by PSP.
+*  Used in the GFX_CTRL.CmdResp.
+*  When PSP GFX I/F is initialized, the flag is set.
+*/
+#define GFX_FLAG_RESPONSE               0x80000000
+
+
+/* TEE Gfx Command IDs for the ring buffer interface. */
+enum psp_gfx_cmd_id
+{
+    GFX_CMD_ID_LOAD_TA      = 0x00000001,   /* load TA */
+    GFX_CMD_ID_UNLOAD_TA    = 0x00000002,   /* unload TA */
+    GFX_CMD_ID_INVOKE_CMD   = 0x00000003,   /* send command to TA */
+    GFX_CMD_ID_LOAD_ASD     = 0x00000004,   /* load ASD Driver */
+    GFX_CMD_ID_SETUP_TMR    = 0x00000005,   /* setup TMR region */
+    GFX_CMD_ID_LOAD_IP_FW   = 0x00000006,   /* load HW IP FW */
+
+};
+
+
+/* Command to load Trusted Application binary into PSP OS. */
+struct psp_gfx_cmd_load_ta
+{
+    uint32_t        app_phy_addr_lo;        /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */
+    uint32_t        app_phy_addr_hi;        /* bits [63:32] of the physical address of the TA binary */
+    uint32_t        app_len;                /* length of the TA binary in bytes */
+    uint32_t        cmd_buf_phy_addr_lo;    /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */
+    uint32_t        cmd_buf_phy_addr_hi;    /* bits [63:32] of the physical address of CMD buffer */
+    uint32_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
+
+    /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
+    *       for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
+    *       of using global persistent buffer.
+    */
+};
+
+
+/* Command to Unload Trusted Application binary from PSP OS. */
+struct psp_gfx_cmd_unload_ta
+{
+    uint32_t        session_id;          /* Session ID of the loaded TA to be unloaded */
+
+};
+
+
+/* Shared buffers for InvokeCommand.
+*/
+struct psp_gfx_buf_desc
+{
+    uint32_t        buf_phy_addr_lo;       /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */
+    uint32_t        buf_phy_addr_hi;       /* bits [63:32] of physical address of the buffer */
+    uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
+
+};
+
+/* Max number of descriptors for one shared buffer (in how many different
+*  physical locations one shared buffer can be stored). If buffer is too much
+*  fragmented, error will be returned.
+*/
+#define GFX_BUF_MAX_DESC        64
+
+struct psp_gfx_buf_list
+{
+    uint32_t                num_desc;                    /* number of buffer descriptors in the list */
+    uint32_t                total_size;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
+    struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC];  /* list of buffer descriptors */
+
+    /* total 776 bytes */
+};
+
+/* Command to execute InvokeCommand entry point of the TA. */
+struct psp_gfx_cmd_invoke_cmd
+{
+    uint32_t                session_id;           /* Session ID of the TA to be executed */
+    uint32_t                ta_cmd_id;            /* Command ID to be sent to TA */
+    struct psp_gfx_buf_list buf;                  /* one indirect buffer (scatter/gather list) */
+
+};
+
+
+/* Command to setup TMR region. */
+struct psp_gfx_cmd_setup_tmr
+{
+    uint32_t        buf_phy_addr_lo;       /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */
+    uint32_t        buf_phy_addr_hi;       /* bits [63:32] of physical address of TMR buffer */
+    uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
+
+};
+
+
+/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
+enum psp_gfx_fw_type
+{
+    GFX_FW_TYPE_NONE        = 0,
+    GFX_FW_TYPE_CP_ME       = 1,
+    GFX_FW_TYPE_CP_PFP      = 2,
+    GFX_FW_TYPE_CP_CE       = 3,
+    GFX_FW_TYPE_CP_MEC      = 4,
+    GFX_FW_TYPE_CP_MEC_ME1  = 5,
+    GFX_FW_TYPE_CP_MEC_ME2  = 6,
+    GFX_FW_TYPE_RLC_V       = 7,
+    GFX_FW_TYPE_RLC_G       = 8,
+    GFX_FW_TYPE_SDMA0       = 9,
+    GFX_FW_TYPE_SDMA1       = 10,
+    GFX_FW_TYPE_DMCU_ERAM   = 11,
+    GFX_FW_TYPE_DMCU_ISR    = 12,
+    GFX_FW_TYPE_VCN         = 13,
+    GFX_FW_TYPE_UVD         = 14,
+    GFX_FW_TYPE_VCE         = 15,
+    GFX_FW_TYPE_ISP         = 16,
+    GFX_FW_TYPE_ACP         = 17,
+    GFX_FW_TYPE_SMU         = 18,
+};
+
+/* Command to load HW IP FW. */
+struct psp_gfx_cmd_load_ip_fw
+{
+    uint32_t                fw_phy_addr_lo;    /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */
+    uint32_t                fw_phy_addr_hi;    /* bits [63:32] of physical address of FW location */
+    uint32_t                fw_size;           /* FW buffer size in bytes */
+    enum psp_gfx_fw_type    fw_type;           /* FW type */
+
+};
+
+
+/* All GFX ring buffer commands. */
+union psp_gfx_commands
+{
+    struct psp_gfx_cmd_load_ta          cmd_load_ta;
+    struct psp_gfx_cmd_unload_ta        cmd_unload_ta;
+    struct psp_gfx_cmd_invoke_cmd       cmd_invoke_cmd;
+    struct psp_gfx_cmd_setup_tmr        cmd_setup_tmr;
+    struct psp_gfx_cmd_load_ip_fw       cmd_load_ip_fw;
+
+};
+
+
+/* Structure of GFX Response buffer.
+* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
+* it is separate buffer.
+*/
+struct psp_gfx_resp
+{
+    uint32_t    status;             /* +0  status of command execution */
+    uint32_t    session_id;         /* +4  session ID in response to LoadTa command */
+    uint32_t    fw_addr_lo;         /* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
+    uint32_t    fw_addr_hi;         /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
+
+    uint32_t    reserved[4];
+
+    /* total 32 bytes */
+};
+
+/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
+*  and psp_gfx_rb_frame.cmd_buf_addr_lo.
+*/
+struct psp_gfx_cmd_resp
+{
+    uint32_t        buf_size;           /* +0  total size of the buffer in bytes */
+    uint32_t        buf_version;        /* +4  version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
+    uint32_t        cmd_id;             /* +8  command ID */
+
+    /* These fields are used for RBI only. They are all 0 in GPCOM commands
+    */
+    uint32_t        resp_buf_addr_lo;   /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */
+    uint32_t        resp_buf_addr_hi;   /* +16 bits [63:32] of physical address of response buffer */
+    uint32_t        resp_offset;        /* +20 offset within response buffer */
+    uint32_t        resp_buf_size;      /* +24 total size of the response buffer in bytes */
+
+    union psp_gfx_commands  cmd;        /* +28 command specific structures */
+
+    uint8_t         reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
+
+    /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
+    *        is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
+    */
+    struct psp_gfx_resp     resp;       /* +864 response */
+
+    uint8_t         reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
+
+    /* total size 1024 bytes */
+};
+
+
+#define FRAME_TYPE_DESTROY          1   /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
+
+/* Structure of the Ring Buffer Frame */
+struct psp_gfx_rb_frame
+{
+    uint32_t    cmd_buf_addr_lo;    /* +0  bits [31:0] of physical address of command buffer (must be 4 KB aligned) */
+    uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of physical address of command buffer */
+    uint32_t    cmd_buf_size;       /* +8  command buffer size in bytes */
+    uint32_t    fence_addr_lo;      /* +12 bits [31:0] of physical address of Fence for this frame */
+    uint32_t    fence_addr_hi;      /* +16 bits [63:32] of physical address of Fence for this frame */
+    uint32_t    fence_value;        /* +20 Fence value */
+    uint32_t    sid_lo;             /* +24 bits [31:0] of SID value (used only for RBI frames) */
+    uint32_t    sid_hi;             /* +28 bits [63:32] of SID value (used only for RBI frames) */
+    uint8_t     vmid;               /* +32 VMID value used for mapping of all addresses for this frame */
+    uint8_t     frame_type;         /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
+    uint8_t     reserved1[2];       /* +34 reserved, must be 0 */
+    uint32_t    reserved2[7];       /* +40 reserved, must be 0 */
+    /* total 64 bytes */
+};
+
+#endif /* _PSP_TEE_GFX_IF_H_ */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
new file mode 100644 (file)
index 0000000..49c3844
--- /dev/null
@@ -0,0 +1,507 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+
+#include <linux/firmware.h>
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+#include "psp_v3_1.h"
+
+#include "vega10/soc15ip.h"
+#include "vega10/MP/mp_9_0_offset.h"
+#include "vega10/MP/mp_9_0_sh_mask.h"
+#include "vega10/GC/gc_9_0_offset.h"
+#include "vega10/SDMA0/sdma0_4_0_offset.h"
+#include "vega10/NBIO/nbio_6_1_offset.h"
+
+MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
+MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
+
+#define smnMP1_FIRMWARE_FLAGS 0x3010028
+
+static int
+psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
+{
+       switch(ucode->ucode_id) {
+       case AMDGPU_UCODE_ID_SDMA0:
+               *type = GFX_FW_TYPE_SDMA0;
+               break;
+       case AMDGPU_UCODE_ID_SDMA1:
+               *type = GFX_FW_TYPE_SDMA1;
+               break;
+       case AMDGPU_UCODE_ID_CP_CE:
+               *type = GFX_FW_TYPE_CP_CE;
+               break;
+       case AMDGPU_UCODE_ID_CP_PFP:
+               *type = GFX_FW_TYPE_CP_PFP;
+               break;
+       case AMDGPU_UCODE_ID_CP_ME:
+               *type = GFX_FW_TYPE_CP_ME;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC1:
+               *type = GFX_FW_TYPE_CP_MEC;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC1_JT:
+               *type = GFX_FW_TYPE_CP_MEC_ME1;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC2:
+               *type = GFX_FW_TYPE_CP_MEC;
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC2_JT:
+               *type = GFX_FW_TYPE_CP_MEC_ME2;
+               break;
+       case AMDGPU_UCODE_ID_RLC_G:
+               *type = GFX_FW_TYPE_RLC_G;
+               break;
+       case AMDGPU_UCODE_ID_SMC:
+               *type = GFX_FW_TYPE_SMU;
+               break;
+       case AMDGPU_UCODE_ID_UVD:
+               *type = GFX_FW_TYPE_UVD;
+               break;
+       case AMDGPU_UCODE_ID_VCE:
+               *type = GFX_FW_TYPE_VCE;
+               break;
+       case AMDGPU_UCODE_ID_MAXIMUM:
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+int psp_v3_1_init_microcode(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+       const char *chip_name;
+       char fw_name[30];
+       int err = 0;
+       const struct psp_firmware_header_v1_0 *hdr;
+
+       DRM_DEBUG("\n");
+
+       switch (adev->asic_type) {
+       case CHIP_VEGA10:
+               chip_name = "vega10";
+               break;
+       default: BUG();
+       }
+
+       snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
+       err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
+       if (err)
+               goto out;
+
+       err = amdgpu_ucode_validate(adev->psp.sos_fw);
+       if (err)
+               goto out;
+
+       hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
+       adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version);
+       adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version);
+       adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes);
+       adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) -
+                                       le32_to_cpu(hdr->sos_size_bytes);
+       adev->psp.sys_start_addr = (uint8_t *)hdr +
+                               le32_to_cpu(hdr->header.ucode_array_offset_bytes);
+       adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
+                               le32_to_cpu(hdr->sos_offset_bytes);
+
+       snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
+       err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
+       if (err)
+               goto out;
+
+       err = amdgpu_ucode_validate(adev->psp.asd_fw);
+       if (err)
+               goto out;
+
+       hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
+       adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
+       adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
+       adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
+       adev->psp.asd_start_addr = (uint8_t *)hdr +
+                               le32_to_cpu(hdr->header.ucode_array_offset_bytes);
+
+       return 0;
+out:
+       if (err) {
+               dev_err(adev->dev,
+                       "psp v3.1: Failed to load firmware \"%s\"\n",
+                       fw_name);
+               release_firmware(adev->psp.sos_fw);
+               adev->psp.sos_fw = NULL;
+               release_firmware(adev->psp.asd_fw);
+               adev->psp.asd_fw = NULL;
+       }
+
+       return err;
+}
+
+int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
+{
+       int ret;
+       uint32_t psp_gfxdrv_command_reg = 0;
+       struct amdgpu_bo *psp_sysdrv;
+       void *psp_sysdrv_virt = NULL;
+       uint64_t psp_sysdrv_mem;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t size;
+
+       /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       /*
+        * Create a 1 meg GART memory to store the psp sys driver
+        * binary with a 1 meg aligned address
+        */
+       size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
+               (~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
+
+       ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
+                                     AMDGPU_GEM_DOMAIN_GTT,
+                                     &psp_sysdrv,
+                                     &psp_sysdrv_mem,
+                                     &psp_sysdrv_virt);
+       if (ret)
+               return ret;
+
+       /* Copy PSP System Driver binary to memory */
+       memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size);
+
+       /* Provide the sys driver to bootrom */
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
+              (uint32_t)(psp_sysdrv_mem >> 20));
+       psp_gfxdrv_command_reg = 1 << 16;
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+              psp_gfxdrv_command_reg);
+
+       /* there might be handshake issue with hardware which needs delay */
+       mdelay(20);
+
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+
+       amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt);
+
+       return ret;
+}
+
+int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
+{
+       int ret;
+       unsigned int psp_gfxdrv_command_reg = 0;
+       struct amdgpu_bo *psp_sos;
+       void *psp_sos_virt = NULL;
+       uint64_t psp_sos_mem;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t size;
+
+       /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, false);
+       if (ret)
+               return ret;
+
+       size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) &
+               (~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1));
+
+       ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT,
+                                     AMDGPU_GEM_DOMAIN_GTT,
+                                     &psp_sos,
+                                     &psp_sos_mem,
+                                     &psp_sos_virt);
+       if (ret)
+               return ret;
+
+       /* Copy Secure OS binary to PSP memory */
+       memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size);
+
+       /* Provide the PSP secure OS to bootrom */
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),
+              (uint32_t)(psp_sos_mem >> 20));
+       psp_gfxdrv_command_reg = 2 << 16;
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+              psp_gfxdrv_command_reg);
+
+       /* there might be handshake issue with hardware which needs delay */
+       mdelay(20);
+#if 0
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
+                          RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)),
+                          0, true);
+#endif
+
+       amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt);
+
+       return ret;
+}
+
+int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
+{
+       int ret;
+       uint64_t fw_mem_mc_addr = ucode->mc_addr;
+
+       memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+       cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+       cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
+       cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
+       cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
+
+       ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+       if (ret)
+               DRM_ERROR("Unknown firmware type\n");
+
+       return ret;
+}
+
+int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+       int ret = 0;
+       unsigned int psp_ring_reg = 0;
+       struct psp_ring *ring;
+       struct amdgpu_device *adev = psp->adev;
+
+       ring = &psp->km_ring;
+
+       ring->ring_type = ring_type;
+
+       /* allocate 4k Page of Local Frame Buffer memory for ring */
+       ring->ring_size = 0x1000;
+       ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     &adev->firmware.rbuf,
+                                     &ring->ring_mem_mc_addr,
+                                     (void **)&ring->ring_mem);
+       if (ret) {
+               ring->ring_size = 0;
+               return ret;
+       }
+
+       /* Write low address of the ring to C2PMSG_69 */
+       psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg);
+       /* Write high address of the ring to C2PMSG_70 */
+       psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg);
+       /* Write size of ring to C2PMSG_71 */
+       psp_ring_reg = ring->ring_size;
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg);
+       /* Write the ring initialization command to C2PMSG_64 */
+       psp_ring_reg = ring_type;
+       psp_ring_reg = psp_ring_reg << 16;
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);
+
+       /* there might be handshake issue with hardware which needs delay */
+       mdelay(20);
+
+       /* Wait for response flag (bit 31) in C2PMSG_64 */
+       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+                          0x80000000, 0x8000FFFF, false);
+
+       return ret;
+}
+
+int psp_v3_1_cmd_submit(struct psp_context *psp,
+                       struct amdgpu_firmware_info *ucode,
+                       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+                       int index)
+{
+       unsigned int psp_write_ptr_reg = 0;
+       struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
+       struct psp_ring *ring = &psp->km_ring;
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t ring_size_dw = ring->ring_size / 4;
+       uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+
+       /* KM (GPCOM) prepare write pointer */
+       psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67));
+
+       /* Update KM RB frame pointer to new frame */
+       /* write_frame ptr increments by size of rb_frame in bytes */
+       /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+       if ((psp_write_ptr_reg % ring_size_dw) == 0)
+               write_frame = ring->ring_mem;
+       else
+               write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
+
+       /* Initialize KM RB frame */
+       memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+
+       /* Update KM RB frame */
+       write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
+       write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
+       write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
+       write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
+       write_frame->fence_value = index;
+
+       /* Update the write Pointer in DWORDs */
+       psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+       WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg);
+
+       return 0;
+}
+
+static int
+psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+                 unsigned int *sram_data_reg_offset,
+                 enum AMDGPU_UCODE_ID ucode_id)
+{
+       int ret = 0;
+
+       switch(ucode_id) {
+/* TODO: needs to confirm */
+#if 0
+       case AMDGPU_UCODE_ID_SMC:
+               *sram_offset = 0;
+               *sram_addr_reg_offset = 0;
+               *sram_data_reg_offset = 0;
+               break;
+#endif
+
+       case AMDGPU_UCODE_ID_CP_CE:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_PFP:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_ME:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_MEC1:
+               *sram_offset = 0x10000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_CP_MEC2:
+               *sram_offset = 0x10000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_RLC_G:
+               *sram_offset = 0x2000;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
+               break;
+
+       case AMDGPU_UCODE_ID_SDMA0:
+               *sram_offset = 0x0;
+               *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
+               *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
+               break;
+
+/* TODO: needs to confirm */
+#if 0
+       case AMDGPU_UCODE_ID_SDMA1:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+
+       case AMDGPU_UCODE_ID_UVD:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+
+       case AMDGPU_UCODE_ID_VCE:
+               *sram_offset = ;
+               *sram_addr_reg_offset = ;
+               break;
+#endif
+
+       case AMDGPU_UCODE_ID_MAXIMUM:
+       default:
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}
+
+bool psp_v3_1_compare_sram_data(struct psp_context *psp,
+                               struct amdgpu_firmware_info *ucode,
+                               enum AMDGPU_UCODE_ID ucode_type)
+{
+       int err = 0;
+       unsigned int fw_sram_reg_val = 0;
+       unsigned int fw_sram_addr_reg_offset = 0;
+       unsigned int fw_sram_data_reg_offset = 0;
+       unsigned int ucode_size;
+       uint32_t *ucode_mem = NULL;
+       struct amdgpu_device *adev = psp->adev;
+
+       err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset,
+                               &fw_sram_data_reg_offset, ucode_type);
+       if (err)
+               return false;
+
+       WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
+
+       ucode_size = ucode->ucode_size;
+       ucode_mem = (uint32_t *)ucode->kaddr;
+       while (!ucode_size) {
+               fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
+
+               if (*ucode_mem != fw_sram_reg_val)
+                       return false;
+
+               ucode_mem++;
+               /* 4 bytes */
+               ucode_size -= 4;
+       }
+
+       return true;
+}
+
+bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+       uint32_t reg, reg_val;
+
+       reg_val = (smnMP1_FIRMWARE_FLAGS & 0xffffffff) | 0x03b00000;
+       WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg_val);
+       reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2));
+       if ((reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+            MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+               return true;
+
+       return false;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
new file mode 100644 (file)
index 0000000..e82eff7
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Huang Rui
+ *
+ */
+#ifndef __PSP_V3_1_H__
+#define __PSP_V3_1_H__
+
+#include "amdgpu_psp.h"
+
+enum { PSP_DIRECTORY_TABLE_ENTRIES = 4 };
+enum { PSP_BINARY_ALIGNMENT = 64 };
+enum { PSP_BOOTLOADER_1_MEG_ALIGNMENT = 0x100000 };
+enum { PSP_BOOTLOADER_8_MEM_ALIGNMENT = 0x800000 };
+
+extern int psp_v3_1_init_microcode(struct psp_context *psp);
+extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
+extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
+extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
+                                struct psp_gfx_cmd_resp *cmd);
+extern int psp_v3_1_ring_init(struct psp_context *psp,
+                             enum psp_ring_type ring_type);
+extern int psp_v3_1_cmd_submit(struct psp_context *psp,
+                              struct amdgpu_firmware_info *ucode,
+                              uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+                              int index);
+extern bool psp_v3_1_compare_sram_data(struct psp_context *psp,
+                                      struct amdgpu_firmware_info *ucode,
+                                      enum AMDGPU_UCODE_ID ucode_type);
+extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
+#endif
index a94420d..2ccf44e 100644 (file)
@@ -68,6 +68,7 @@ enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_GMC,
        AMD_IP_BLOCK_TYPE_IH,
        AMD_IP_BLOCK_TYPE_SMC,
+       AMD_IP_BLOCK_TYPE_PSP,
        AMD_IP_BLOCK_TYPE_DCE,
        AMD_IP_BLOCK_TYPE_GFX,
        AMD_IP_BLOCK_TYPE_SDMA,