drm/i915/xelpd: Add Wa_14011503030
authorMatt Roper <matthew.d.roper@intel.com>
Wed, 12 May 2021 04:21:42 +0000 (21:21 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 12 May 2021 23:56:52 +0000 (16:56 -0700)
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-6-matthew.d.roper@intel.com
drivers/gpu/drm/i915/display/intel_display_power.c
drivers/gpu/drm/i915/i915_reg.h

index ec55616..54c6d65 100644 (file)
@@ -5872,6 +5872,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
                      DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
                intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
        }
+
+       /* Wa_14011503030:xelpd */
+       if (DISPLAY_VER(dev_priv) >= 13)
+               intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
 }
 
 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
index 6584ef0..9f73f13 100644 (file)
@@ -7785,6 +7785,8 @@ enum {
 #define  GEN8_GT_BCS_IRQ               (1 << 1)
 #define  GEN8_GT_RCS_IRQ               (1 << 0)
 
+#define XELPD_DISPLAY_ERR_FATAL_MASK   _MMIO(0x4421c)
+
 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))