radv,radeonsi: make sure to emit GRBM_GFX_INDEX before SQ select registers
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 14 Sep 2023 13:49:05 +0000 (15:49 +0200)
committerMarge Bot <emma+marge@anholt.net>
Mon, 18 Sep 2023 07:07:31 +0000 (07:07 +0000)
This was missing, but not sure if it was required given that only the
first SE is currently sampled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25240>

src/amd/vulkan/radv_spm.c
src/gallium/drivers/radeonsi/si_perfcounter.c

index bdea139..ab620f9 100644 (file)
@@ -65,7 +65,11 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu
    const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
    struct ac_spm *spm = &device->spm;
 
-   radeon_check_space(device->ws, cs, spm->num_used_sq_block_sel * 3);
+   radeon_check_space(device->ws, cs, 3 + spm->num_used_sq_block_sel * 3);
+
+   radeon_set_uconfig_reg(
+      cs, R_030800_GRBM_GFX_INDEX,
+      S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1) | S_030800_SE_INDEX(0));
 
    for (uint32_t b = 0; b < spm->num_used_sq_block_sel; b++) {
       struct ac_spm_block_select *sq_block_sel = &spm->sq_block_sel[b];
index 42a3f9f..de0fa34 100644 (file)
@@ -733,6 +733,11 @@ si_emit_spm_counters(struct si_context *sctx, struct radeon_cmdbuf *cs)
 
    radeon_begin(cs);
 
+   radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
+                          S_030800_SH_BROADCAST_WRITES(1) |
+                          S_030800_INSTANCE_BROADCAST_WRITES(1) |
+                          S_030800_SE_INDEX(0));
+
    for (uint32_t b = 0; b < spm->num_used_sq_block_sel; b++) {
       struct ac_spm_block_select *sq_block_sel = &spm->sq_block_sel[b];
       const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0];