int (*get_compute_partition_mode)(struct amdgpu_device *adev);
u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,
u32 *supp_modes);
- void (*set_compute_partition_mode)(struct amdgpu_device *adev,
- enum amdgpu_gfx_partition mode);
};
struct amdgpu_nbio {
return px;
}
-static void nbio_v7_9_set_compute_partition_mode(struct amdgpu_device *adev,
- enum amdgpu_gfx_partition mode)
-{
- u32 tmp;
-
- /* SPX=0, DPX=1, TPX=2, QPX=3, CPX=4 */
- tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
- tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
- PARTITION_MODE, mode);
-
- WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS, tmp);
-}
-
static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
u32 *supp_modes)
{
.ih_control = nbio_v7_9_ih_control,
.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
- .set_compute_partition_mode = nbio_v7_9_set_compute_partition_mode,
.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
.init_registers = nbio_v7_9_init_registers,
};