omap5912osk \
omap730p2 \
openrd_base \
+ openrd_client \
+ openrd_ultimate \
rd6281a \
sbc2410x \
scb9328 \
define this to a list of base addresses for each (supported)
port. See e.g. include/configs/versatile.h
+ CONFIG_PL011_SERIAL_RLCR
+
+ Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
+ have separate receive and transmit line control registers. Set
+ this variable to initialize the extra register.
+
+ CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+ On some platforms (e.g. U8500) U-Boot is loaded by a second stage
+ boot loader that has already initialized the UART. Define this
+ variable to flush the UART at init time.
+
- Console Interface:
Depending on board, define exactly one serial port
}
struct mx3_cpu_type mx31_cpu_type[] = {
- { .srev = 0x00, .v = "1.0" },
- { .srev = 0x10, .v = "1.1" },
- { .srev = 0x11, .v = "1.1" },
- { .srev = 0x12, .v = "1.15" },
- { .srev = 0x13, .v = "1.15" },
- { .srev = 0x14, .v = "1.2" },
- { .srev = 0x15, .v = "1.2" },
- { .srev = 0x28, .v = "2.0" },
- { .srev = 0x29, .v = "2.0" },
+ { .srev = 0x00, .v = 0x10 },
+ { .srev = 0x10, .v = 0x11 },
+ { .srev = 0x11, .v = 0x11 },
+ { .srev = 0x12, .v = 0x1F },
+ { .srev = 0x13, .v = 0x1F },
+ { .srev = 0x14, .v = 0x12 },
+ { .srev = 0x15, .v = 0x12 },
+ { .srev = 0x28, .v = 0x20 },
+ { .srev = 0x29, .v = 0x20 },
};
-char *get_cpu_rev(void)
+u32 get_cpu_rev(void)
{
u32 i, srev;
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev)
return mx31_cpu_type[i].v;
- return "unknown";
+
+ return srev | 0x8000;
}
char *get_reset_cause(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
- printf("CPU: Freescale i.MX31 rev %s at %d MHz.",
- get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000);
+ u32 srev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.",
+ (srev & 0xF0) >> 4, (srev & 0x0F),
+ ((srev & 0x8000) ? " unknown" : ""),
+ mx31_get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#ifndef _ASM_ARCH_KW88F6281_H
#define _ASM_ARCH_KW88F6281_H
-/* SOC specific definations */
+/* SOC specific definitions */
#define KW88F6281_REGS_PHYS_BASE 0xf1000000
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
-/* TCLK Core Clock defination*/
-#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+#endif
#endif /* _ASM_ARCH_KW88F6281_H */
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
+void mxc_hw_watchdog_enable(void);
#endif /* __ASM_ARCH_CLOCK_H */
struct mx3_cpu_type {
u8 srev;
- char *v;
+ u32 v;
};
#define IOMUX_PADNUM_MASK 0x1ff
LIB = $(obj)lib$(BOARD).o
-COBJS := openrd_base.o
+COBJS := openrd.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#include <miiphy.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>
-#include "openrd_base.h"
+#include "openrd.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* arch number of board
*/
+#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
+#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
+#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
}
#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
{
u16 reg;
u16 devadr;
- char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* reset the phy */
miiphy_reset(name, devadr);
- printf("88E1116 Initialized on %s\n", name);
+ printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+ /* Kirkwood ethernet driver is written with the assumption that in case
+ * of multiple PHYs, their addresses are consecutive. But unfortunately
+ * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+ miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+ defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ /* configure and initialize both PHY's */
+ mv_phy_init("egiga1");
+#endif
}
#endif /* CONFIG_RESET_PHY_R */
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) |
- DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */
#endif
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ mxc_hw_watchdog_reset();
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
return 0;
}
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ mxc_hw_watchdog_enable();
+#endif
+ return 0;
+}
+
int checkboard(void)
{
printf("Board: MX31PDK\n");
mgcoge2un arm arm926ejs km_arm keymile kirkwood
guruplug arm arm926ejs - Marvell kirkwood
mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
-openrd_base arm arm926ejs - Marvell kirkwood
+openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
+openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT
+openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE
rd6281a arm arm926ejs - Marvell kirkwood
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <mxc_gpio.h>
+#include <errno.h>
/* GPIO port description */
static unsigned long gpio_ports[] = {
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
- return 1;
+ return -EINVAL;
gpio &= 0x1f;
u32 l;
if (port >= ARRAY_SIZE(gpio_ports))
- return -1;
+ return -EINVAL;
gpio &= 0x1f;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
+ unsigned int lcr;
+
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+ /* Empty RX fifo if necessary */
+ if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
+ while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
+ readl(®s->dr);
+ }
+#endif
/* First, disable everything */
writel(0, ®s->pl011_cr);
writel(fraction, ®s->pl011_fbrd);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
- writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
- ®s->pl011_lcrh);
-
+ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+ writel(lcr, ®s->pl011_lcrh);
+
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
+ int i;
+
+ /*
+ * Program receive line control register after waiting
+ * 10 bus cycles. Delay be writing to readonly register
+ * 10 times
+ */
+ for (i = 0; i < 10; i++)
+ writel(lcr, ®s->fr);
+
+ writel(lcr, ®s->pl011_rlcr);
+ }
+#endif
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
®s->pl011_cr);
u32 pl010_lcrl; /* 0x10 Line control register, low byte */
u32 pl010_cr; /* 0x14 Control register */
u32 fr; /* 0x18 Flag register (Read only) */
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ u32 pl011_rlcr; /* 0x1c Receive line control register */
+#else
u32 reserved;
+#endif
u32 ilpr; /* 0x20 IrDA low-power counter register */
u32 pl011_ibrd; /* 0x24 Integer baud rate register */
u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* ====> Include platform Common Definitions */
+#include <asm/arch/config.h>
+
/*
* DRAM Banks configuration, Custom config can be done in <board>.h
*/
#endif
#endif /* CONFIG_NR_DRAM_BANKS */
-/* ====> Include platform Common Definations */
-#include <asm/arch/config.h>
-
-/* ====> Include driver Common Definations */
+/* ====> Include driver Common Definitions */
/*
* Common NAND configuration
*/
#define CONFIG_MXC_UART 1
#define CONFIG_SYS_MX31_UART1 1
+#define CONFIG_HW_WATCHDOG
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
*/
#undef CONFIG_CMD_IMLS
+#define BOARD_LATE_INIT
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
* MA 02110-1301 USA
*/
-#ifndef _CONFIG_OPENRD_BASE_H
-#define _CONFIG_OPENRD_BASE_H
+#ifndef _CONFIG_OPENRD_H
+#define _CONFIG_OPENRD_H
/*
* Version number information
*/
-#define CONFIG_IDENT_STRING "\nOpenRD_base"
+#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
+#else
+# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+# define CONFIG_IDENT_STRING "\nOpenRD-Client"
+# else
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+# define CONFIG_IDENT_STRING "\nOpenRD-Base"
+# else
+# error Unknown OpenRD board specified
+# endif
+# endif
+#endif
/*
* High Level Configuration Options (easy to change)
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
#include <config_cmd_default.h>
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_DHCP
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
-#define CONFIG_PHY_BASE_ADR 0x8
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+# else
+# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
+# endif
+# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+# define CONFIG_PHY_BASE_ADR 0x0
+# define PHY_NO "88E1121"
+# else
+# define CONFIG_PHY_BASE_ADR 0x8
+# define PHY_NO "88E1116"
+# endif
#endif /* CONFIG_CMD_NET */
/*
#if defined(CONFIG_CMD_NFS)
case NFS:
#endif
- case NETCONS:
case TFTP:
if (NetServerIP == 0) {
puts ("*** ERROR: `serverip' not set\n");
defined(CONFIG_CMD_DNS)
common:
#endif
+ /* Fall through */
+ case NETCONS:
if (NetOurIP == 0) {
puts ("*** ERROR: `ipaddr' not set\n");
return (1);
projects / platform / kernel / u-boot.git / commitdiff