SANDBOX_FLASH_BLOCK_LEN = 512,
};
-enum cmd_phase {
- PHASE_START,
- PHASE_DATA,
- PHASE_STATUS,
-};
-
enum {
STRINGID_MANUFACTURER = 1,
STRINGID_PRODUCT,
int alloc_len;
int transfer_len;
int read_len;
- enum cmd_phase phase;
+ enum scsi_cmd_phase phase;
u32 tag;
int fd;
loff_t file_size;
return -EPROTONOSUPPORT;
}
- priv->phase = priv->transfer_len ? PHASE_DATA : PHASE_STATUS;
+ priv->phase = priv->transfer_len ? SCSIPH_DATA : SCSIPH_STATUS;
return 0;
}
switch (ep) {
case SANDBOX_FLASH_EP_OUT:
switch (priv->phase) {
- case PHASE_START:
+ case SCSIPH_START:
priv->alloc_len = 0;
priv->read_len = 0;
if (priv->error || len != UMASS_BBB_CBW_SIZE ||
priv->tag = cbw->dCBWTag;
return handle_ufi_command(plat, priv, cbw->CBWCDB,
cbw->bCDBLength);
- case PHASE_DATA:
+ case SCSIPH_DATA:
debug("data out\n");
break;
default:
}
case SANDBOX_FLASH_EP_IN:
switch (priv->phase) {
- case PHASE_DATA:
+ case SCSIPH_DATA:
debug("data in, len=%x, alloc_len=%x, priv->read_len=%x\n",
len, priv->alloc_len, priv->read_len);
if (priv->read_len) {
return -EIO;
priv->read_len -= len / SANDBOX_FLASH_BLOCK_LEN;
if (!priv->read_len)
- priv->phase = PHASE_STATUS;
+ priv->phase = SCSIPH_STATUS;
} else {
if (priv->alloc_len && len > priv->alloc_len)
len = priv->alloc_len;
if (len > sizeof(priv->buff))
len = sizeof(priv->buff);
memcpy(buff, priv->buff, len);
- priv->phase = PHASE_STATUS;
+ priv->phase = SCSIPH_STATUS;
}
return len;
- case PHASE_STATUS:
+ case SCSIPH_STATUS:
debug("status in, len=%x\n", len);
if (len > sizeof(priv->status))
len = sizeof(priv->status);
memcpy(buff, &priv->status, len);
- priv->phase = PHASE_START;
+ priv->phase = SCSIPH_START;
return len;
default:
break;
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/**
+ * enum scsi_cmd_phase - current phase of the SCSI protocol
+ *
+ * @SCSIPH_START: Start phase
+ * @SCSIPH_DATA: Data phase
+ * @SCSIPH_STATUS: Status phase
+ */
+enum scsi_cmd_phase {
+ SCSIPH_START,
+ SCSIPH_DATA,
+ SCSIPH_STATUS,
+};
+
+/**
* struct scsi_plat - stores information about SCSI controller
*
* @base: Controller base address