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ARM: rmobile: Update R8A7795 PFC and GPIO tables
authorMarek Vasut <marek.vasut@gmail.com>
Sat, 13 May 2017 13:57:31 +0000 (15:57 +0200)
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Sun, 21 May 2017 19:38:25 +0000 (04:38 +0900)
Sync the PFC and GPIO tables with the latest 3.5.3 release from
Renesas . This adds ES2.0 support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h patch | blob | history
arch/arm/mach-rmobile/pfc-r8a7795.c patch | blob | history

diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
index 63e156d..554063a 100644 (file)
--- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
@@ -2,7 +2,7 @@
  * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h
  *     This file defines pin function control of gpio.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -13,6 +13,8 @@
  * GPIO_FN_xx - GPIO used to select pin function
  * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
  */
+
+/* V2(ES2.0) */
 enum {
        GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
        GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
@@ -26,6 +28,7 @@ enum {
        GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
        GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
        GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+       GPIO_GP_1_28,
 
        GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
        GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
@@ -81,6 +84,7 @@ enum {
        GPIO_GFN_D0,
 
        /* GPSR1 */
+       GPIO_GFN_CLKOUT,
        GPIO_GFN_EX_WAIT0_A,
        GPIO_GFN_WE1x,
        GPIO_GFN_WE0x,
@@ -146,23 +150,23 @@ enum {
        GPIO_GFN_SD0_CLK,
 
        /* GPSR4 */
-       GPIO_FN_SD3_DS,
+       GPIO_GFN_SD3_DS,
        GPIO_GFN_SD3_DAT7,
        GPIO_GFN_SD3_DAT6,
        GPIO_GFN_SD3_DAT5,
        GPIO_GFN_SD3_DAT4,
-       GPIO_FN_SD3_DAT3,
-       GPIO_FN_SD3_DAT2,
-       GPIO_FN_SD3_DAT1,
-       GPIO_FN_SD3_DAT0,
-       GPIO_FN_SD3_CMD,
-       GPIO_FN_SD3_CLK,
+       GPIO_GFN_SD3_DAT3,
+       GPIO_GFN_SD3_DAT2,
+       GPIO_GFN_SD3_DAT1,
+       GPIO_GFN_SD3_DAT0,
+       GPIO_GFN_SD3_CMD,
+       GPIO_GFN_SD3_CLK,
        GPIO_GFN_SD2_DS,
        GPIO_GFN_SD2_DAT3,
        GPIO_GFN_SD2_DAT2,
        GPIO_GFN_SD2_DAT1,
        GPIO_GFN_SD2_DAT0,
-       GPIO_FN_SD2_CMD,
+       GPIO_GFN_SD2_CMD,
        GPIO_GFN_SD2_CLK,
 
        /* GPSR5 */
@@ -194,8 +198,8 @@ enum {
        GPIO_GFN_SCK0,
 
        /* GPSR6 */
-       GPIO_GFN_USB31_OVC,
-       GPIO_GFN_USB31_PWEN,
+       GPIO_GFN_USB3_OVC,
+       GPIO_GFN_USB3_PWEN,
        GPIO_GFN_USB30_OVC,
        GPIO_GFN_USB30_PWEN,
        GPIO_GFN_USB1_OVC,
@@ -224,8 +228,8 @@ enum {
        GPIO_GFN_SSI_SDATA2_A,
        GPIO_GFN_SSI_SDATA1_A,
        GPIO_GFN_SSI_SDATA0,
-       GPIO_GFN_SSI_WS0129,
-       GPIO_GFN_SSI_SCK0129,
+       GPIO_GFN_SSI_WS01239,
+       GPIO_GFN_SSI_SCK01239,
 
        /* GPSR7 */
        GPIO_FN_HDMI1_CEC,
@@ -237,7 +241,7 @@ enum {
        GPIO_IFN_AVB_MDC,
        GPIO_FN_MSIOF2_SS2_C,
        GPIO_IFN_AVB_MAGIC,
-       GPIO_FN_MSIOF2_S1_C,
+       GPIO_FN_MSIOF2_SS1_C,
        GPIO_FN_SCK4_A,
        GPIO_IFN_AVB_PHY_INT,
        GPIO_FN_MSIOF2_SYNC_C,
@@ -248,6 +252,7 @@ enum {
        GPIO_IFN_AVB_AVTP_MATCH_A,
        GPIO_FN_MSIOF2_RXD_C,
        GPIO_FN_CTS4x_A,
+       GPIO_FN_FSCLKST2x_A,
        GPIO_IFN_AVB_AVTP_CAPTURE_A,
        GPIO_FN_MSIOF2_TXD_C,
        GPIO_FN_RTS4x_TANS_A,
@@ -257,50 +262,53 @@ enum {
        GPIO_FN_VI4_DATA0_B,
        GPIO_FN_CAN0_TX_B,
        GPIO_FN_CANFD0_TX_B,
+       GPIO_FN_MSIOF3_SS2_E,
        GPIO_IFN_IRQ1,
        GPIO_FN_QPOLA,
        GPIO_FN_DU_DISP,
        GPIO_FN_VI4_DATA1_B,
        GPIO_FN_CAN0_RX_B,
        GPIO_FN_CANFD0_RX_B,
+       GPIO_FN_MSIOF3_SS1_E,
 
        /* IPSR1 */
        GPIO_IFN_IRQ2,
        GPIO_FN_QCPV_QDE,
        GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,
        GPIO_FN_VI4_DATA2_B,
+       GPIO_FN_MSIOF3_SYNC_E,
        GPIO_FN_PWM3_B,
        GPIO_IFN_IRQ3,
        GPIO_FN_QSTVB_QVE,
        GPIO_FN_A25,
        GPIO_FN_DU_DOTCLKOUT1,
        GPIO_FN_VI4_DATA3_B,
+       GPIO_FN_MSIOF3_SCK_E,
        GPIO_FN_PWM4_B,
        GPIO_IFN_IRQ4,
        GPIO_FN_QSTH_QHS,
        GPIO_FN_A24,
        GPIO_FN_DU_EXHSYNC_DU_HSYNC,
        GPIO_FN_VI4_DATA4_B,
+       GPIO_FN_MSIOF3_RXD_E,
        GPIO_FN_PWM5_B,
        GPIO_IFN_IRQ5,
        GPIO_FN_QSTB_QHE,
        GPIO_FN_A23,
        GPIO_FN_DU_EXVSYNC_DU_VSYNC,
        GPIO_FN_VI4_DATA5_B,
+       GPIO_FN_FSCLKST2x_B,
+       GPIO_FN_MSIOF3_TXD_E,
        GPIO_FN_PWM6_B,
        GPIO_IFN_PWM0,
        GPIO_FN_AVB_AVTP_PPS,
-       GPIO_FN_A22,
        GPIO_FN_VI4_DATA6_B,
        GPIO_FN_IECLK_B,
        GPIO_IFN_PWM1_A,
-       GPIO_FN_A21,
        GPIO_FN_HRX3_D,
        GPIO_FN_VI4_DATA7_B,
        GPIO_FN_IERX_B,
        GPIO_IFN_PWM2_A,
-       GPIO_FN_PWMFSW0,
-       GPIO_FN_A20,
        GPIO_FN_HTX3_D,
        GPIO_FN_IETX_B,
        GPIO_IFN_A0,
@@ -382,7 +390,6 @@ enum {
        GPIO_FN_SCL6_A,
        GPIO_FN_AVB_AVTP_CAPTURE_B,
        GPIO_FN_PWM2_B,
-       GPIO_FN_SPV_EVEN,
        GPIO_IFN_A12,
        GPIO_FN_LCDOUT12,
        GPIO_FN_MSIOF3_SCK_C,
@@ -588,67 +595,94 @@ enum {
        GPIO_IFN_SD1_CLK,
        GPIO_FN_MSIOF1_SCK_G,
        GPIO_FN_SIM0_CLK_A,
-
        GPIO_IFN_SD1_CMD,
        GPIO_FN_MSIOF1_SYNC_G,
+       GPIO_FN_NFCEx_B,
        GPIO_FN_SIM0_D_A,
        GPIO_FN_STP_IVCXO27_1_B,
-
        GPIO_IFN_SD1_DAT0,
        GPIO_FN_SD2_DAT4,
        GPIO_FN_MSIOF1_RXD_G,
+       GPIO_FN_NFWPx_B,
        GPIO_FN_TS_SCK1_B,
        GPIO_FN_STP_ISCLK_1_B,
-
        GPIO_IFN_SD1_DAT1,
        GPIO_FN_SD2_DAT5,
        GPIO_FN_MSIOF1_TXD_G,
+       GPIO_FN_NFDATA14_B,
        GPIO_FN_TS_SPSYNC1_B,
        GPIO_FN_STP_ISSYNC_1_B,
-
        GPIO_IFN_SD1_DAT2,
        GPIO_FN_SD2_DAT6,
        GPIO_FN_MSIOF1_SS1_G,
+       GPIO_FN_NFDATA15_B,
        GPIO_FN_TS_SDAT1_B,
        GPIO_FN_STP_IOD_1_B,
        GPIO_IFN_SD1_DAT3,
        GPIO_FN_SD2_DAT7,
        GPIO_FN_MSIOF1_SS2_G,
+       GPIO_FN_NFRBx_B,
        GPIO_FN_TS_SDEN1_B,
        GPIO_FN_STP_ISEN_1_B,
 
        /* IPSR9 */
        GPIO_IFN_SD2_CLK,
-       GPIO_FN_SCKZ_A,
+       GPIO_FN_NFDATA8,
+       GPIO_IFN_SD2_CMD,
+       GPIO_FN_NFDATA9,
        GPIO_IFN_SD2_DAT0,
-       GPIO_FN_MTSx_A,
+       GPIO_FN_NFDATA10,
        GPIO_IFN_SD2_DAT1,
-       GPIO_FN_STMx_A,
+       GPIO_FN_NFDATA11,
        GPIO_IFN_SD2_DAT2,
-       GPIO_FN_MDATA_A,
+       GPIO_FN_NFDATA12,
        GPIO_IFN_SD2_DAT3,
-       GPIO_FN_SDATA_A,
+       GPIO_FN_NFDATA13,
        GPIO_IFN_SD2_DS,
+       GPIO_FN_NFALE,
        GPIO_FN_SATA_DEVSLP_B,
-       GPIO_FN_VSP_A,
+       GPIO_IFN_SD3_CLK,
+       GPIO_FN_NFWEx,
+
+       /* IPSR10 */
+       GPIO_IFN_SD3_CMD,
+       GPIO_FN_NFREx,
+       GPIO_IFN_SD3_DAT0,
+       GPIO_FN_NFDATA0,
+       GPIO_IFN_SD3_DAT1,
+       GPIO_FN_NFDATA1,
+       GPIO_IFN_SD3_DAT2,
+       GPIO_FN_NFDATA2,
+       GPIO_IFN_SD3_DAT3,
+       GPIO_FN_NFDATA3,
        GPIO_IFN_SD3_DAT4,
        GPIO_FN_SD2_CD_A,
+       GPIO_FN_NFDATA4,
        GPIO_IFN_SD3_DAT5,
        GPIO_FN_SD2_WP_A,
-
-       /* IPSR10 */
+       GPIO_FN_NFDATA5,
        GPIO_IFN_SD3_DAT6,
        GPIO_FN_SD3_CD,
+       GPIO_FN_NFDATA6,
+
+       /* IPSR11 */
        GPIO_IFN_SD3_DAT7,
        GPIO_FN_SD3_WP,
+       GPIO_FN_NFDATA7,
+       GPIO_IFN_SD3_DS,
+       GPIO_FN_NFCLE,
        GPIO_IFN_SD0_CD,
+       GPIO_FN_NFDATA14_A,
        GPIO_FN_SCL2_B,
        GPIO_FN_SIM0_RST_A,
        GPIO_IFN_SD0_WP,
+       GPIO_FN_NFDATA15_A,
        GPIO_FN_SDA2_B,
        GPIO_IFN_SD1_CD,
+       GPIO_FN_NFRBx_A,
        GPIO_FN_SIM0_CLK_B,
        GPIO_IFN_SD1_WP,
+       GPIO_FN_NFCEx_A,
        GPIO_FN_SIM0_D_B,
        GPIO_IFN_SCK0,
        GPIO_FN_HSCK1_B,
@@ -656,16 +690,17 @@ enum {
        GPIO_FN_AUDIO_CLKC_B,
        GPIO_FN_SDA2_A,
        GPIO_FN_SIM0_RST_B,
-       GPIO_FN_STP_OPWM__C,
+       GPIO_FN_STP_OPWM_0_C,
        GPIO_FN_RIF0_CLK_B,
        GPIO_FN_ADICHS2,
+       GPIO_FN_SCK5_B,
        GPIO_IFN_RX0,
        GPIO_FN_HRX1_B,
        GPIO_FN_TS_SCK0_C,
        GPIO_FN_STP_ISCLK_0_C,
        GPIO_FN_RIF0_D0_B,
 
-       /* IPSR11 */
+       /* IPSR12 */
        GPIO_IFN_TX0,
        GPIO_FN_HTX1_B,
        GPIO_FN_TS_SPSYNC0_C,
@@ -690,7 +725,7 @@ enum {
        GPIO_IFN_RX1_A,
        GPIO_FN_HRX1_A,
        GPIO_FN_TS_SDAT0_C,
-       GPIO_FN_STP_IDS_0_C,
+       GPIO_FN_STP_ISD_0_C,
        GPIO_FN_RIF1_CLK_C,
        GPIO_IFN_TX1_A,
        GPIO_FN_HTX1_A,
@@ -719,21 +754,19 @@ enum {
        GPIO_FN_RIF1_CLK_B,
        GPIO_FN_ADICLK,
 
-       /* IPSR12 */
+       /* IPSR13 */
        GPIO_IFN_TX2_A,
        GPIO_FN_SD2_CD_B,
        GPIO_FN_SCL1_A,
-       GPIO_FN_RSD_CLK_B,
        GPIO_FN_FMCLK_A,
        GPIO_FN_RIF1_D1_C,
-       GPIO_FN_FSO_CFE_0_B,
+       GPIO_FN_FSO_CFE_0x,
        GPIO_IFN_RX2_A,
        GPIO_FN_SD2_WP_B,
        GPIO_FN_SDA1_A,
-       GPIO_FN_RDS_DATA_B,
-       GPIO_FN_RMIN_A,
+       GPIO_FN_FMIN_A,
        GPIO_FN_RIF1_SYNC_C,
-       GPIO_FN_FSO_CEF_1_B,
+       GPIO_FN_FSO_CFE_1x,
        GPIO_IFN_HSCK0,
        GPIO_FN_MSIOF1_SCK_D,
        GPIO_FN_AUDIO_CLKB_A,
@@ -741,21 +774,19 @@ enum {
        GPIO_FN_TS_SCK0_D,
        GPIO_FN_STP_ISCLK_0_D,
        GPIO_FN_RIF0_CLK_C,
-       GPIO_FN_AD_CLK,
+       GPIO_FN_RX5_B,
        GPIO_IFN_HRX0,
        GPIO_FN_MSIOF1_RXD_D,
-       GPIO_FN_SS1_SDATA2_B,
+       GPIO_FN_SSI_SDATA2_B,
        GPIO_FN_TS_SDEN0_D,
        GPIO_FN_STP_ISEN_0_D,
        GPIO_FN_RIF0_D0_C,
-       GPIO_FN_AD_DI,
        GPIO_IFN_HTX0,
        GPIO_FN_MSIOF1_TXD_D,
        GPIO_FN_SSI_SDATA9_B,
        GPIO_FN_TS_SDAT0_D,
        GPIO_FN_STP_ISD_0_D,
        GPIO_FN_RIF0_D1_C,
-       GPIO_FN_AD_DO,
        GPIO_IFN_HCTS0x,
        GPIO_FN_RX2_B,
        GPIO_FN_MSIOF1_SYNC_D,
@@ -764,7 +795,6 @@ enum {
        GPIO_FN_STP_ISSYNC_0_D,
        GPIO_FN_RIF0_SYNC_C,
        GPIO_FN_AUDIO_CLKOUT1_A,
-       GPIO_FN_AD_NSCx,
        GPIO_IFN_HRTS0x,
        GPIO_FN_TX2_B,
        GPIO_FN_MSIOF1_SS1_D,
@@ -774,22 +804,23 @@ enum {
        GPIO_FN_AUDIO_CLKOUT2_A,
        GPIO_IFN_MSIOF0_SYNC,
        GPIO_FN_AUDIO_CLKOUT_A,
+       GPIO_FN_TX5_B,
+       GPIO_FN_BPFCLK_D,
 
-       /* IPSR13 */
+       /* IPSR14 */
        GPIO_IFN_MSIOF0_SS1,
-       GPIO_FN_RX5,
+       GPIO_FN_RX5_A,
+       GPIO_FN_NFWPx_A,
        GPIO_FN_AUDIO_CLKA_C,
        GPIO_FN_SSI_SCK2_A,
-       GPIO_FN_RDS_CLK_A,
        GPIO_FN_STP_IVCXO27_0_C,
        GPIO_FN_AUDIO_CLKOUT3_A,
        GPIO_FN_TCLK1_B,
        GPIO_IFN_MSIOF0_SS2,
-       GPIO_FN_TX5,
+       GPIO_FN_TX5_A,
        GPIO_FN_MSIOF1_SS2_D,
        GPIO_FN_AUDIO_CLKC_A,
        GPIO_FN_SSI_WS2_A,
-       GPIO_FN_RDS_DATA_A,
        GPIO_FN_STP_OPWM_0_D,
        GPIO_FN_AUDIO_CLKOUT_D,
        GPIO_FN_SPEEDIN_B,
@@ -803,17 +834,17 @@ enum {
        GPIO_IFN_MLB_DAT,
        GPIO_FN_TX1_B,
        GPIO_FN_MSIOF1_RXD_F,
-       GPIO_IFN_SSI_SCK0129,
+       GPIO_IFN_SSI_SCK01239,
        GPIO_FN_MSIOF1_TXD_F,
        GPIO_FN_MOUT0,
-       GPIO_IFN_SSI_WS0129,
+       GPIO_IFN_SSI_WS01239,
        GPIO_FN_MSIOF1_SS1_F,
        GPIO_FN_MOUT1,
        GPIO_IFN_SSI_SDATA0,
        GPIO_FN_MSIOF1_SS2_F,
        GPIO_FN_MOUT2,
 
-       /* IPSR14 */
+       /* IPSR15 */
        GPIO_IFN_SSI_SDATA1_A,
        GPIO_FN_MOUT5,
        GPIO_IFN_SSI_SDATA2_A,
@@ -855,17 +886,13 @@ enum {
        GPIO_FN_RIF0_D0_A,
        GPIO_FN_RIF2_D1_A,
 
-       /* IPSR15 */
+       /* IPSR16 */
        GPIO_IFN_SSI_SCK6,
-       GPIO_FN_USB2_PWEN,
        GPIO_FN_SIM0_RST_D,
-       GPIO_FN_RDS_CLK_C,
        GPIO_IFN_SSI_WS6,
-       GPIO_FN_USB2_OVC,
        GPIO_FN_SIM0_D_D,
        GPIO_IFN_SSI_SDATA6,
        GPIO_FN_SIM0_CLK_D,
-       GPIO_FN_RSD_DATA_C,
        GPIO_FN_SATA_DEVSLP_A,
        GPIO_IFN_SSI_SCK78,
        GPIO_FN_HRX2_B,
@@ -877,7 +904,7 @@ enum {
        GPIO_IFN_SSI_WS78,
        GPIO_FN_HTX2_B,
        GPIO_FN_MSIOF1_SYNC_C,
-       GPIO_FN_TS_SDT1_A,
+       GPIO_FN_TS_SDAT1_A,
        GPIO_FN_STP_ISD_1_A,
        GPIO_FN_RIF1_SYNC_A,
        GPIO_FN_RIF3_SYNC_A,
@@ -885,7 +912,7 @@ enum {
        GPIO_FN_HCTS2x_B,
        GPIO_FN_MSIOF1_RXD_C,
        GPIO_FN_TS_SDEN1_A,
-       GPIO_FN_STP_IEN_1_A,
+       GPIO_FN_STP_ISEN_1_A,
        GPIO_FN_RIF1_D0_A,
        GPIO_FN_RIF3_D0_A,
        GPIO_FN_TCLK2_A,
@@ -895,7 +922,7 @@ enum {
        GPIO_FN_TS_SPSYNC1_A,
        GPIO_FN_STP_ISSYNC_1_A,
        GPIO_FN_RIF1_D1_A,
-       GPIO_FN_EIF3_D1_A,
+       GPIO_FN_RIF3_D1_A,
        GPIO_IFN_SSI_SDATA9_A,
        GPIO_FN_HSCK2_B,
        GPIO_FN_MSIOF1_SS1_C,
@@ -903,31 +930,29 @@ enum {
        GPIO_FN_SSI_WS1_B,
        GPIO_FN_SCK1,
        GPIO_FN_STP_IVCXO27_1_A,
-       GPIO_FN_SCK5,
+       GPIO_FN_SCK5_A,
 
-       /* IPSR16 */
+       /* IPSR17 */
        GPIO_IFN_AUDIO_CLKA_A,
        GPIO_FN_CC5_OSCOUT,
        GPIO_IFN_AUDIO_CLKB_B,
        GPIO_FN_SCIF_CLK_A,
-       GPIO_FN_DVC_MUTE,
        GPIO_FN_STP_IVCXO27_1_D,
        GPIO_FN_REMOCON_A,
        GPIO_FN_TCLK1_A,
-       GPIO_FN_VSP_B,
        GPIO_IFN_USB0_PWEN,
        GPIO_FN_SIM0_RST_C,
        GPIO_FN_TS_SCK1_D,
        GPIO_FN_STP_ISCLK_1_D,
        GPIO_FN_BPFCLK_B,
        GPIO_FN_RIF3_CLK_B,
-       GPIO_FN_SCKZ_B,
+       GPIO_FN_HSCK2_C,
        GPIO_IFN_USB0_OVC,
        GPIO_FN_SIM0_D_C,
        GPIO_FN_TS_SDAT1_D,
        GPIO_FN_STP_ISD_1_D,
        GPIO_FN_RIF3_SYNC_B,
-       GPIO_FN_VSP_C,
+       GPIO_FN_HRX2_C,
        GPIO_IFN_USB1_PWEN,
        GPIO_FN_SIM0_CLK_C,
        GPIO_FN_SSI_SCK1_A,
@@ -935,9 +960,8 @@ enum {
        GPIO_FN_STP_ISCLK_0_E,
        GPIO_FN_FMCLK_B,
        GPIO_FN_RIF2_CLK_B,
-       GPIO_FN_MTSx_B,
        GPIO_FN_SPEEDIN_A,
-       GPIO_FN_VSP_D,
+       GPIO_FN_HTX2_C,
        GPIO_IFN_USB1_OVC,
        GPIO_FN_MSIOF1_SS2_C,
        GPIO_FN_SSI_WS1_A,
@@ -945,8 +969,8 @@ enum {
        GPIO_FN_STP_ISD_0_E,
        GPIO_FN_FMIN_B,
        GPIO_FN_RIF2_SYNC_B,
-       GPIO_FN_STMx_B,
        GPIO_FN_REMOCON_B,
+       GPIO_FN_HCTS2x_C,
        GPIO_IFN_USB30_PWEN,
        GPIO_FN_AUDIO_CLKOUT_B,
        GPIO_FN_SSI_SCK2_B,
@@ -954,9 +978,10 @@ enum {
        GPIO_FN_STP_ISEN_1_D,
        GPIO_FN_STP_OPWM_0_E,
        GPIO_FN_RIF3_D0_B,
-       GPIO_FN_MDATA_B,
        GPIO_FN_TCLK2_B,
        GPIO_FN_TPU0TO0,
+       GPIO_FN_BPFCLK_C,
+       GPIO_FN_HRTS2x_C,
        GPIO_IFN_USB30_OVC,
        GPIO_FN_AUDIO_CLKOUT1_B,
        GPIO_FN_SSI_WS2_B,
@@ -964,25 +989,28 @@ enum {
        GPIO_FN_STP_ISSYNC_1_D,
        GPIO_FN_STP_IVCXO27_0_E,
        GPIO_FN_RIF3_D1_B,
-       GPIO_FN_SDATA_B,
-       GPIO_FN_RSO_TOE_B,
+       GPIO_FN_FSO_TOEx,
        GPIO_FN_TPU0TO1,
 
-       /* IPSR17 */
-       GPIO_IFN_USB31_PWEN,
+       /* IPSR18 */
+       GPIO_IFN_USB3_PWEN,
        GPIO_FN_AUDIO_CLKOUT2_B,
-       GPIO_FN_SI_SCK9_B,
+       GPIO_FN_SSI_SCK9_B,
        GPIO_FN_TS_SDEN0_E,
        GPIO_FN_STP_ISEN_0_E,
        GPIO_FN_RIF2_D0_B,
        GPIO_FN_TPU0TO2,
-       GPIO_IFN_USB31_OVC,
+       GPIO_FN_FMCLK_C,
+       GPIO_FN_FMCLK_D,
+       GPIO_IFN_USB3_OVC,
        GPIO_FN_AUDIO_CLKOUT3_B,
        GPIO_FN_SSI_WS9_B,
        GPIO_FN_TS_SPSYNC0_E,
        GPIO_FN_STP_ISSYNC_0_E,
        GPIO_FN_RIF2_D1_B,
        GPIO_FN_TPU0TO3,
+       GPIO_FN_FMIN_C,
+       GPIO_FN_FMIN_D,
 };
 
 #endif /* __ASM_R8A7795_GPIO_H__ */
diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c
index 65d66a0..4446093 100644 (file)
--- a/arch/arm/mach-rmobile/pfc-r8a7795.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7795.c
@@ -2,7 +2,7 @@
  * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c
  *     This file is r8a7795 processor support - PFC hardware block.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -24,6 +24,19 @@
        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
        PORT_10(fn, pfx##2, sfx)
 
+#define CPU_32_PORT_29(fn, pfx, sfx)                           \
+       PORT_10(fn, pfx, sfx),                                  \
+       PORT_10(fn, pfx##1, sfx),                               \
+       PORT_1(fn, pfx##20, sfx),                               \
+       PORT_1(fn, pfx##21, sfx),                               \
+       PORT_1(fn, pfx##22, sfx),                               \
+       PORT_1(fn, pfx##23, sfx),                               \
+       PORT_1(fn, pfx##24, sfx),                               \
+       PORT_1(fn, pfx##25, sfx),                               \
+       PORT_1(fn, pfx##26, sfx),                               \
+       PORT_1(fn, pfx##27, sfx),                               \
+       PORT_1(fn, pfx##28, sfx)
+
 #define CPU_32_PORT_28(fn, pfx, sfx)                           \
        PORT_10(fn, pfx, sfx),                                  \
        PORT_10(fn, pfx##1, sfx),                               \
@@ -91,7 +104,7 @@
                GP5[26] - [31],
                GP7[4] - [31] */
 
-#define CPU_ALL_PORT(fn, pfx, sfx)             \
+#define ES_CPU_ALL_PORT(fn, pfx, sfx)          \
        CPU_32_PORT_16(fn, pfx##_0_, sfx),      \
        CPU_32_PORT_28(fn, pfx##_1_, sfx),      \
        CPU_32_PORT_15(fn, pfx##_2_, sfx),      \
@@ -101,6 +114,16 @@
        CPU_32_PORT(fn, pfx##_6_, sfx),         \
        CPU_32_PORT_4(fn, pfx##_7_, sfx)
 
+#define CPU_ALL_PORT(fn, pfx, sfx)             \
+       CPU_32_PORT_16(fn, pfx##_0_, sfx),      \
+       CPU_32_PORT_29(fn, pfx##_1_, sfx),      \
+       CPU_32_PORT_15(fn, pfx##_2_, sfx),      \
+       CPU_32_PORT_16(fn, pfx##_3_, sfx),      \
+       CPU_32_PORT_18(fn, pfx##_4_, sfx),      \
+       CPU_32_PORT_26(fn, pfx##_5_, sfx),      \
+       CPU_32_PORT(fn, pfx##_6_, sfx),         \
+       CPU_32_PORT_4(fn, pfx##_7_, sfx)
+
 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
 #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,   \
                                       GP##pfx##_IN, GP##pfx##_OUT)
@@ -169,6 +192,7 @@ enum {
        GFN_D0,
 
        /* GPSR1 */
+       GFN_CLKOUT,
        GFN_EX_WAIT0_A,
        GFN_WE1x,
        GFN_WE0x,
@@ -234,23 +258,23 @@ enum {
        GFN_SD0_CLK,
 
        /* GPSR4 */
-       FN_SD3_DS,
+       GFN_SD3_DS,
        GFN_SD3_DAT7,
        GFN_SD3_DAT6,
        GFN_SD3_DAT5,
        GFN_SD3_DAT4,
-       FN_SD3_DAT3,
-       FN_SD3_DAT2,
-       FN_SD3_DAT1,
-       FN_SD3_DAT0,
-       FN_SD3_CMD,
-       FN_SD3_CLK,
+       GFN_SD3_DAT3,
+       GFN_SD3_DAT2,
+       GFN_SD3_DAT1,
+       GFN_SD3_DAT0,
+       GFN_SD3_CMD,
+       GFN_SD3_CLK,
        GFN_SD2_DS,
        GFN_SD2_DAT3,
        GFN_SD2_DAT2,
        GFN_SD2_DAT1,
        GFN_SD2_DAT0,
-       FN_SD2_CMD,
+       GFN_SD2_CMD,
        GFN_SD2_CLK,
 
        /* GPSR5 */
@@ -282,8 +306,8 @@ enum {
        GFN_SCK0,
 
        /* GPSR6 */
-       GFN_USB31_OVC,
-       GFN_USB31_PWEN,
+       GFN_USB3_OVC,
+       GFN_USB3_PWEN,
        GFN_USB30_OVC,
        GFN_USB30_PWEN,
        GFN_USB1_OVC,
@@ -312,8 +336,8 @@ enum {
        GFN_SSI_SDATA2_A,
        GFN_SSI_SDATA1_A,
        GFN_SSI_SDATA0,
-       GFN_SSI_WS0129,
-       GFN_SSI_SCK0129,
+       GFN_SSI_WS01239,
+       GFN_SSI_SCK01239,
 
        /* GPSR7 */
        FN_HDMI1_CEC,
@@ -325,7 +349,7 @@ enum {
        IFN_AVB_MDC,
        FN_MSIOF2_SS2_C,
        IFN_AVB_MAGIC,
-       FN_MSIOF2_S1_C,
+       FN_MSIOF2_SS1_C,
        FN_SCK4_A,
        IFN_AVB_PHY_INT,
        FN_MSIOF2_SYNC_C,
@@ -336,6 +360,7 @@ enum {
        IFN_AVB_AVTP_MATCH_A,
        FN_MSIOF2_RXD_C,
        FN_CTS4x_A,
+       FN_FSCLKST2x_A,
        IFN_AVB_AVTP_CAPTURE_A,
        FN_MSIOF2_TXD_C,
        FN_RTS4x_TANS_A,
@@ -345,50 +370,50 @@ enum {
        FN_VI4_DATA0_B,
        FN_CAN0_TX_B,
        FN_CANFD0_TX_B,
+       FN_MSIOF3_SS2_E,
        IFN_IRQ1,
        FN_QPOLA,
        FN_DU_DISP,
        FN_VI4_DATA1_B,
        FN_CAN0_RX_B,
        FN_CANFD0_RX_B,
+       FN_MSIOF3_SS1_E,
 
        /* IPSR1 */
        IFN_IRQ2,
        FN_QCPV_QDE,
        FN_DU_EXODDF_DU_ODDF_DISP_CDE,
        FN_VI4_DATA2_B,
+       FN_MSIOF3_SYNC_E,
        FN_PWM3_B,
        IFN_IRQ3,
        FN_QSTVB_QVE,
-       FN_A25,
        FN_DU_DOTCLKOUT1,
        FN_VI4_DATA3_B,
+       FN_MSIOF3_SCK_E,
        FN_PWM4_B,
        IFN_IRQ4,
        FN_QSTH_QHS,
-       FN_A24,
        FN_DU_EXHSYNC_DU_HSYNC,
        FN_VI4_DATA4_B,
+       FN_MSIOF3_RXD_E,
        FN_PWM5_B,
        IFN_IRQ5,
        FN_QSTB_QHE,
-       FN_A23,
        FN_DU_EXVSYNC_DU_VSYNC,
        FN_VI4_DATA5_B,
+       FN_FSCLKST2x_B,
+       FN_MSIOF3_TXD_E,
        FN_PWM6_B,
        IFN_PWM0,
        FN_AVB_AVTP_PPS,
-       FN_A22,
        FN_VI4_DATA6_B,
        FN_IECLK_B,
        IFN_PWM1_A,
-       FN_A21,
        FN_HRX3_D,
        FN_VI4_DATA7_B,
        FN_IERX_B,
        IFN_PWM2_A,
-       FN_PWMFSW0,
-       FN_A20,
        FN_HTX3_D,
        FN_IETX_B,
        IFN_A0,
@@ -470,7 +495,6 @@ enum {
        FN_SCL6_A,
        FN_AVB_AVTP_CAPTURE_B,
        FN_PWM2_B,
-       FN_SPV_EVEN,
        IFN_A12,
        FN_LCDOUT12,
        FN_MSIOF3_SCK_C,
@@ -676,67 +700,94 @@ enum {
        IFN_SD1_CLK,
        FN_MSIOF1_SCK_G,
        FN_SIM0_CLK_A,
-
        IFN_SD1_CMD,
        FN_MSIOF1_SYNC_G,
+       FN_NFCEx_B,
        FN_SIM0_D_A,
        FN_STP_IVCXO27_1_B,
-
        IFN_SD1_DAT0,
        FN_SD2_DAT4,
        FN_MSIOF1_RXD_G,
+       FN_NFWPx_B,
        FN_TS_SCK1_B,
        FN_STP_ISCLK_1_B,
-
        IFN_SD1_DAT1,
        FN_SD2_DAT5,
        FN_MSIOF1_TXD_G,
+       FN_NFDATA14_B,
        FN_TS_SPSYNC1_B,
        FN_STP_ISSYNC_1_B,
-
        IFN_SD1_DAT2,
        FN_SD2_DAT6,
        FN_MSIOF1_SS1_G,
+       FN_NFDATA15_B,
        FN_TS_SDAT1_B,
        FN_STP_IOD_1_B,
        IFN_SD1_DAT3,
        FN_SD2_DAT7,
        FN_MSIOF1_SS2_G,
+       FN_NFRBx_B,
        FN_TS_SDEN1_B,
        FN_STP_ISEN_1_B,
 
        /* IPSR9 */
        IFN_SD2_CLK,
-       FN_SCKZ_A,
+       FN_NFDATA8,
+       IFN_SD2_CMD,
+       FN_NFDATA9,
        IFN_SD2_DAT0,
-       FN_MTSx_A,
+       FN_NFDATA10,
        IFN_SD2_DAT1,
-       FN_STMx_A,
+       FN_NFDATA11,
        IFN_SD2_DAT2,
-       FN_MDATA_A,
+       FN_NFDATA12,
        IFN_SD2_DAT3,
-       FN_SDATA_A,
+       FN_NFDATA13,
        IFN_SD2_DS,
+       FN_NFALE,
        FN_SATA_DEVSLP_B,
-       FN_VSP_A,
+       IFN_SD3_CLK,
+       FN_NFWEx,
+
+       /* IPSR10 */
+       IFN_SD3_CMD,
+       FN_NFREx,
+       IFN_SD3_DAT0,
+       FN_NFDATA0,
+       IFN_SD3_DAT1,
+       FN_NFDATA1,
+       IFN_SD3_DAT2,
+       FN_NFDATA2,
+       IFN_SD3_DAT3,
+       FN_NFDATA3,
        IFN_SD3_DAT4,
        FN_SD2_CD_A,
+       FN_NFDATA4,
        IFN_SD3_DAT5,
        FN_SD2_WP_A,
-
-       /* IPSR10 */
+       FN_NFDATA5,
        IFN_SD3_DAT6,
        FN_SD3_CD,
+       FN_NFDATA6,
+
+       /* IPSR11 */
        IFN_SD3_DAT7,
        FN_SD3_WP,
+       FN_NFDATA7,
+       IFN_SD3_DS,
+       FN_NFCLE,
        IFN_SD0_CD,
+       FN_NFDATA14_A,
        FN_SCL2_B,
        FN_SIM0_RST_A,
        IFN_SD0_WP,
+       FN_NFDATA15_A,
        FN_SDA2_B,
        IFN_SD1_CD,
+       FN_NFRBx_A,
        FN_SIM0_CLK_B,
        IFN_SD1_WP,
+       FN_NFCEx_A,
        FN_SIM0_D_B,
        IFN_SCK0,
        FN_HSCK1_B,
@@ -744,16 +795,17 @@ enum {
        FN_AUDIO_CLKC_B,
        FN_SDA2_A,
        FN_SIM0_RST_B,
-       FN_STP_OPWM__C,
+       FN_STP_OPWM_0_C,
        FN_RIF0_CLK_B,
        FN_ADICHS2,
+       FN_SCK5_B,
        IFN_RX0,
        FN_HRX1_B,
        FN_TS_SCK0_C,
        FN_STP_ISCLK_0_C,
        FN_RIF0_D0_B,
 
-       /* IPSR11 */
+       /* IPSR12 */
        IFN_TX0,
        FN_HTX1_B,
        FN_TS_SPSYNC0_C,
@@ -778,7 +830,7 @@ enum {
        IFN_RX1_A,
        FN_HRX1_A,
        FN_TS_SDAT0_C,
-       FN_STP_IDS_0_C,
+       FN_STP_ISD_0_C,
        FN_RIF1_CLK_C,
        IFN_TX1_A,
        FN_HTX1_A,
@@ -807,21 +859,19 @@ enum {
        FN_RIF1_CLK_B,
        FN_ADICLK,
 
-       /* IPSR12 */
+       /* IPSR13 */
        IFN_TX2_A,
        FN_SD2_CD_B,
        FN_SCL1_A,
-       FN_RSD_CLK_B,
        FN_FMCLK_A,
        FN_RIF1_D1_C,
-       FN_FSO_CFE_0_B,
+       FN_FSO_CFE_0x,
        IFN_RX2_A,
        FN_SD2_WP_B,
        FN_SDA1_A,
-       FN_RDS_DATA_B,
-       FN_RMIN_A,
+       FN_FMIN_A,
        FN_RIF1_SYNC_C,
-       FN_FSO_CEF_1_B,
+       FN_FSO_CFE_1x,
        IFN_HSCK0,
        FN_MSIOF1_SCK_D,
        FN_AUDIO_CLKB_A,
@@ -829,21 +879,19 @@ enum {
        FN_TS_SCK0_D,
        FN_STP_ISCLK_0_D,
        FN_RIF0_CLK_C,
-       FN_AD_CLK,
+       FN_RX5_B,
        IFN_HRX0,
        FN_MSIOF1_RXD_D,
-       FN_SS1_SDATA2_B,
+       FN_SSI_SDATA2_B,
        FN_TS_SDEN0_D,
        FN_STP_ISEN_0_D,
        FN_RIF0_D0_C,
-       FN_AD_DI,
        IFN_HTX0,
        FN_MSIOF1_TXD_D,
        FN_SSI_SDATA9_B,
        FN_TS_SDAT0_D,
        FN_STP_ISD_0_D,
        FN_RIF0_D1_C,
-       FN_AD_DO,
        IFN_HCTS0x,
        FN_RX2_B,
        FN_MSIOF1_SYNC_D,
@@ -852,7 +900,6 @@ enum {
        FN_STP_ISSYNC_0_D,
        FN_RIF0_SYNC_C,
        FN_AUDIO_CLKOUT1_A,
-       FN_AD_NSCx,
        IFN_HRTS0x,
        FN_TX2_B,
        FN_MSIOF1_SS1_D,
@@ -862,22 +909,23 @@ enum {
        FN_AUDIO_CLKOUT2_A,
        IFN_MSIOF0_SYNC,
        FN_AUDIO_CLKOUT_A,
+       FN_TX5_B,
+       FN_BPFCLK_D,
 
-       /* IPSR13 */
+       /* IPSR14 */
        IFN_MSIOF0_SS1,
-       FN_RX5,
+       FN_RX5_A,
+       FN_NFWPx_A,
        FN_AUDIO_CLKA_C,
        FN_SSI_SCK2_A,
-       FN_RDS_CLK_A,
        FN_STP_IVCXO27_0_C,
        FN_AUDIO_CLKOUT3_A,
        FN_TCLK1_B,
        IFN_MSIOF0_SS2,
-       FN_TX5,
+       FN_TX5_A,
        FN_MSIOF1_SS2_D,
        FN_AUDIO_CLKC_A,
        FN_SSI_WS2_A,
-       FN_RDS_DATA_A,
        FN_STP_OPWM_0_D,
        FN_AUDIO_CLKOUT_D,
        FN_SPEEDIN_B,
@@ -891,17 +939,17 @@ enum {
        IFN_MLB_DAT,
        FN_TX1_B,
        FN_MSIOF1_RXD_F,
-       IFN_SSI_SCK0129,
+       IFN_SSI_SCK01239,
        FN_MSIOF1_TXD_F,
        FN_MOUT0,
-       IFN_SSI_WS0129,
+       IFN_SSI_WS01239,
        FN_MSIOF1_SS1_F,
        FN_MOUT1,
        IFN_SSI_SDATA0,
        FN_MSIOF1_SS2_F,
        FN_MOUT2,
 
-       /* IPSR14 */
+       /* IPSR15 */
        IFN_SSI_SDATA1_A,
        FN_MOUT5,
        IFN_SSI_SDATA2_A,
@@ -943,16 +991,13 @@ enum {
        FN_RIF0_D0_A,
        FN_RIF2_D1_A,
 
+       /* IPSR16 */
        IFN_SSI_SCK6,
-       FN_USB2_PWEN,
        FN_SIM0_RST_D,
-       FN_RDS_CLK_C,
        IFN_SSI_WS6,
-       FN_USB2_OVC,
        FN_SIM0_D_D,
        IFN_SSI_SDATA6,
        FN_SIM0_CLK_D,
-       FN_RSD_DATA_C,
        FN_SATA_DEVSLP_A,
        IFN_SSI_SCK78,
        FN_HRX2_B,
@@ -964,7 +1009,7 @@ enum {
        IFN_SSI_WS78,
        FN_HTX2_B,
        FN_MSIOF1_SYNC_C,
-       FN_TS_SDT1_A,
+       FN_TS_SDAT1_A,
        FN_STP_ISD_1_A,
        FN_RIF1_SYNC_A,
        FN_RIF3_SYNC_A,
@@ -972,7 +1017,7 @@ enum {
        FN_HCTS2x_B,
        FN_MSIOF1_RXD_C,
        FN_TS_SDEN1_A,
-       FN_STP_IEN_1_A,
+       FN_STP_ISEN_1_A,
        FN_RIF1_D0_A,
        FN_RIF3_D0_A,
        FN_TCLK2_A,
@@ -982,7 +1027,7 @@ enum {
        FN_TS_SPSYNC1_A,
        FN_STP_ISSYNC_1_A,
        FN_RIF1_D1_A,
-       FN_EIF3_D1_A,
+       FN_RIF3_D1_A,
        IFN_SSI_SDATA9_A,
        FN_HSCK2_B,
        FN_MSIOF1_SS1_C,
@@ -990,31 +1035,29 @@ enum {
        FN_SSI_WS1_B,
        FN_SCK1,
        FN_STP_IVCXO27_1_A,
-       FN_SCK5,
+       FN_SCK5_A,
 
-       /* IPSR16 */
+       /* IPSR17 */
        IFN_AUDIO_CLKA_A,
        FN_CC5_OSCOUT,
        IFN_AUDIO_CLKB_B,
        FN_SCIF_CLK_A,
-       FN_DVC_MUTE,
        FN_STP_IVCXO27_1_D,
        FN_REMOCON_A,
        FN_TCLK1_A,
-       FN_VSP_B,
        IFN_USB0_PWEN,
        FN_SIM0_RST_C,
        FN_TS_SCK1_D,
        FN_STP_ISCLK_1_D,
        FN_BPFCLK_B,
        FN_RIF3_CLK_B,
-       FN_SCKZ_B,
+       FN_HSCK2_C,
        IFN_USB0_OVC,
        FN_SIM0_D_C,
        FN_TS_SDAT1_D,
        FN_STP_ISD_1_D,
        FN_RIF3_SYNC_B,
-       FN_VSP_C,
+       FN_HRX2_C,
        IFN_USB1_PWEN,
        FN_SIM0_CLK_C,
        FN_SSI_SCK1_A,
@@ -1022,9 +1065,8 @@ enum {
        FN_STP_ISCLK_0_E,
        FN_FMCLK_B,
        FN_RIF2_CLK_B,
-       FN_MTSx_B,
        FN_SPEEDIN_A,
-       FN_VSP_D,
+       FN_HTX2_C,
        IFN_USB1_OVC,
        FN_MSIOF1_SS2_C,
        FN_SSI_WS1_A,
@@ -1032,8 +1074,8 @@ enum {
        FN_STP_ISD_0_E,
        FN_FMIN_B,
        FN_RIF2_SYNC_B,
-       FN_STMx_B,
        FN_REMOCON_B,
+       FN_HCTS2x_C,
        IFN_USB30_PWEN,
        FN_AUDIO_CLKOUT_B,
        FN_SSI_SCK2_B,
@@ -1041,9 +1083,10 @@ enum {
        FN_STP_ISEN_1_D,
        FN_STP_OPWM_0_E,
        FN_RIF3_D0_B,
-       FN_MDATA_B,
        FN_TCLK2_B,
        FN_TPU0TO0,
+       FN_BPFCLK_C,
+       FN_HRTS2x_C,
        IFN_USB30_OVC,
        FN_AUDIO_CLKOUT1_B,
        FN_SSI_WS2_B,
@@ -1051,135 +1094,167 @@ enum {
        FN_STP_ISSYNC_1_D,
        FN_STP_IVCXO27_0_E,
        FN_RIF3_D1_B,
-       FN_SDATA_B,
-       FN_RSO_TOE_B,
+       FN_FSO_TOEx,
        FN_TPU0TO1,
 
-       /* IPSR17 */
-       IFN_USB31_PWEN,
+       /* IPSR18 */
+       IFN_USB3_PWEN,
        FN_AUDIO_CLKOUT2_B,
-       FN_SI_SCK9_B,
+       FN_SSI_SCK9_B,
        FN_TS_SDEN0_E,
        FN_STP_ISEN_0_E,
        FN_RIF2_D0_B,
        FN_TPU0TO2,
-       IFN_USB31_OVC,
+       FN_FMCLK_C,
+       FN_FMCLK_D,
+       IFN_USB3_OVC,
        FN_AUDIO_CLKOUT3_B,
        FN_SSI_WS9_B,
        FN_TS_SPSYNC0_E,
        FN_STP_ISSYNC_0_E,
        FN_RIF2_D1_B,
        FN_TPU0TO3,
+       FN_FMIN_C,
+       FN_FMIN_D,
 
        /* MOD_SEL0 */
+       /* sel_msiof3[3](0,1,2,3,4) */
        FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
        FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
+       FN_SEL_MSIOF3_4,
+       /* sel_msiof2[2](0,1,2,3) */
        FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
        FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
+       /* sel_msiof1[3](0,1,2,3,4,5,6) */
        FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
        FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
        FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
        FN_SEL_MSIOF1_6,
+       /* sel_lbsc[1](0,1) */
        FN_SEL_LBSC_0, FN_SEL_LBSC_1,
+       /* sel_iebus[1](0,1) */
        FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
-       FN_SEL_I2C6_0, FN_SEL_I2C6_1,
-       FN_SEL_I2C6_2,
+       /* sel_i2c2[1](0,1) */
        FN_SEL_I2C2_0, FN_SEL_I2C2_1,
+       /* sel_i2c1[1](0,1) */
        FN_SEL_I2C1_0, FN_SEL_I2C1_1,
+       /* sel_hscif4[1](0,1) */
        FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
+       /* sel_hscif3[2](0,1,2,3) */
        FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
        FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
-       FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+       /* sel_hscif1[1](0,1) */
        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-       FN_SEL_FSO_1,
-       FN_SEL_FM_0, FN_SEL_FM_1,
+       /* reserved[1] */
+       /* sel_hscif2[2](0,1,2) */
+       FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+       FN_SEL_HSCIF2_2,
+       /* sel_etheravb[1](0,1) */
        FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
+       /* sel_drif3[1](0,1) */
        FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
+       /* sel_drif2[1](0,1) */
        FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
+       /* sel_drif1[2](0,1,2) */
        FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
        FN_SEL_DRIF1_2,
+       /* sel_drif0[2](0,1,2) */
        FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
        FN_SEL_DRIF0_2,
+       /* sel_canfd0[1](0,1) */
        FN_SEL_CANFD_0, FN_SEL_CANFD_1,
-       FN_SEL_ADG_0, FN_SEL_ADG_1,
-       FN_SEL_ADG_2, FN_SEL_ADG_3,
-       FN_SEL_5LINE_0, FN_SEL_5LINE_1,
+       /* sel_adg_a[2](0,1,2) */
+       FN_SEL_ADG_A_0, FN_SEL_ADG_A_1,
+       FN_SEL_ADG_A_2,
+       /* reserved[3]*/
 
        /* MOD_SEL1 */
-       FN_SEL_TSIF1_0,
-       FN_SEL_TSIF1_1,
-       FN_SEL_TSIF1_2,
-       FN_SEL_TSIF1_3,
-       FN_SEL_TSIF0_0,
-       FN_SEL_TSIF0_1,
-       FN_SEL_TSIF0_2,
-       FN_SEL_TSIF0_3,
+       /* sel_tsif1[2](0,1,2,3) */
+       FN_SEL_TSIF1_0, FN_SEL_TSIF1_1,
+       FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
+       /* sel_tsif0[3](0,1,2,3,4) */
+       FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+       FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
        FN_SEL_TSIF0_4,
-       FN_SEL_TIMER_TMU_0,
-       FN_SEL_TIMER_TMU_1,
-       FN_SEL_SSP1_1_0,
-       FN_SEL_SSP1_1_1,
-       FN_SEL_SSP1_1_2,
-       FN_SEL_SSP1_1_3,
-       FN_SEL_SSP1_0_0,
-       FN_SEL_SSP1_0_1,
-       FN_SEL_SSP1_0_2,
-       FN_SEL_SSP1_0_3,
+       /* sel_timer_tmu1[1](0,1) */
+       FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,
+       /* sel_ssp1_1[2](0,1,2,3) */
+       FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,
+       FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,
+       /* sel_ssp1_0[3](0,1,2,3,4) */
+       FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
+       FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,
        FN_SEL_SSP1_0_4,
-       FN_SEL_SSI_0,
-       FN_SEL_SSI_1,
-       FN_SEL_SPEED_PULSE_IF_0,
-       FN_SEL_SPEED_PULSE_IF_1,
-       FN_SEL_SIMCARD_0,
-       FN_SEL_SIMCARD_1,
-       FN_SEL_SIMCARD_2,
-       FN_SEL_SIMCARD_3,
-       FN_SEL_SDHI2_0,
-       FN_SEL_SDHI2_1,
-       FN_SEL_SCIF4_0,
-       FN_SEL_SCIF4_1,
+       /* sel_ssi1[1](0,1) */
+       FN_SEL_SSI_0, FN_SEL_SSI_1,
+       /* sel_speed_pulse_if[1](0,1) */
+       FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
+       /* sel_simcard[2](0,1,2,3) */
+       FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,
+       FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
+       /* sel_sdhi2[1](0,1) */
+       FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
+       /* sel_scif4[2](0,1,2) */
+       FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
        FN_SEL_SCIF4_2,
-       FN_SEL_SCIF3_0,
-       FN_SEL_SCIF3_1,
-       FN_SEL_SCIF2_0,
-       FN_SEL_SCIF2_1,
-       FN_SEL_SCIF1_0,
-       FN_SEL_SCIF1_1,
-       FN_SEL_SCIF_0,
-       FN_SEL_SCIF_1,
-       FN_SEL_REMOCON_0,
-       FN_SEL_REMOCON_1,
-       FN_SEL_RDS_0,
-       FN_SEL_RDS_1,
-       FN_SEL_RDS_2,
-       FN_SEL_RCAN_0,
-       FN_SEL_RCAN_1,
-       FN_SEL_PWM6_0,
-       FN_SEL_PWM6_1,
-       FN_SEL_PWM5_0,
-       FN_SEL_PWM5_1,
-       FN_SEL_PWM4_0,
-       FN_SEL_PWM4_1,
-       FN_SEL_PWM3_0,
-       FN_SEL_PWM3_1,
-       FN_SEL_PWM2_0,
-       FN_SEL_PWM2_1,
-       FN_SEL_PWM1_0,
-       FN_SEL_PWM1_1,
+       /* sel_scif3[1](0,1) */
+       FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+       /* sel_scif2[1](0,1) */
+       FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
+       /* sel_scif1[1](0,1) */
+       FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
+       /* sel_scif[1](0,1) */
+       FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+       /* sel_remocon[1](0,1) */
+       FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
+       /* reserved[8..7] */
+       /* sel_rcan0[1](0,1) */
+       FN_SEL_RCAN_0, FN_SEL_RCAN_1,
+       /* sel_pwm6[1](0,1) */
+       FN_SEL_PWM6_0, FN_SEL_PWM6_1,
+       /* sel_pwm5[1](0,1) */
+       FN_SEL_PWM5_0, FN_SEL_PWM5_1,
+       /* sel_pwm4[1](0,1) */
+       FN_SEL_PWM4_0, FN_SEL_PWM4_1,
+       /* sel_pwm3[1](0,1) */
+       FN_SEL_PWM3_0, FN_SEL_PWM3_1,
+       /* sel_pwm2[1](0,1) */
+       FN_SEL_PWM2_0, FN_SEL_PWM2_1,
+       /* sel_pwm1[1](0,1) */
+       FN_SEL_PWM1_0, FN_SEL_PWM1_1,
 
        /* MOD_SEL2 */
-       FN_I2C_SEL_5_0,
-       FN_I2C_SEL_5_1,
-       FN_I2C_SEL_3_0,
-       FN_I2C_SEL_3_1,
-       FN_I2C_SEL_0_0,
-       FN_I2C_SEL_0_1,
-       FN_SEL_VSP_0,
-       FN_SEL_VSP_1,
-       FN_SEL_VSP_2,
-       FN_SEL_VSP_3,
-       FN_SEL_VIN4_0,
-       FN_SEL_VIN4_1,
+       /* i2c_sel_5[1](0,1) */
+       FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
+       /* i2c_sel_3[1](0,1) */
+       FN_I2C_SEL_3_0, FN_I2C_SEL_3_1,
+       /* i2c_sel_0[1](0,1) */
+       FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
+       /* sel_fm[2](0,1,2,3) */
+       FN_SEL_FM_0, FN_SEL_FM_1,
+       FN_SEL_FM_2, FN_SEL_FM_3,
+       /* sel_scif5[1](0,1) */
+       FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+       /* sel_i2c6[3](0,1,2) */
+       FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+       FN_SEL_I2C6_2,
+       /* sel_ndfc[1](0,1) */
+       FN_SEL_NDFC_0, FN_SEL_NDFC_1,
+       /* sel_ssi2[1](0,1) */
+       FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+       /* sel_ssi9[1](0,1) */
+       FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+       /* sel_timer_tmu2[1](0,1) */
+       FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,
+       /* sel_adg_b[1](0,1) */
+       FN_SEL_ADG_B_0, FN_SEL_ADG_B_1,
+       /* sel_adg_c[1](0,1) */
+       FN_SEL_ADG_C_0, FN_SEL_ADG_C_1,
+       /* reserved[16..16] */
+       /* reserved[15..8] */
+       /* reserved[7..1] */
+       /* sel_vin4[1](0,1) */
+       FN_SEL_VIN4_0, FN_SEL_VIN4_1,
 
        PINMUX_FUNCTION_END,
 
@@ -1204,6 +1279,7 @@ enum {
        D0_GMARK,
 
        /* GPSR1 */
+       CLKOUT_GMARK,
        EX_WAIT0_A_GMARK,
        WE1x_GMARK,
        WE0x_GMARK,
@@ -1269,23 +1345,23 @@ enum {
        SD0_CLK_GMARK,
 
        /* GPSR4 */
-       SD3_DS_MARK,
+       SD3_DS_GMARK,
        SD3_DAT7_GMARK,
        SD3_DAT6_GMARK,
        SD3_DAT5_GMARK,
        SD3_DAT4_GMARK,
-       SD3_DAT3_MARK,
-       SD3_DAT2_MARK,
-       SD3_DAT1_MARK,
-       SD3_DAT0_MARK,
-       SD3_CMD_MARK,
-       SD3_CLK_MARK,
+       SD3_DAT3_GMARK,
+       SD3_DAT2_GMARK,
+       SD3_DAT1_GMARK,
+       SD3_DAT0_GMARK,
+       SD3_CMD_GMARK,
+       SD3_CLK_GMARK,
        SD2_DS_GMARK,
        SD2_DAT3_GMARK,
        SD2_DAT2_GMARK,
        SD2_DAT1_GMARK,
        SD2_DAT0_GMARK,
-       SD2_CMD_MARK,
+       SD2_CMD_GMARK,
        SD2_CLK_GMARK,
 
        /* GPSR5 */
@@ -1317,8 +1393,8 @@ enum {
        SCK0_GMARK,
 
        /* GPSR6 */
-       USB31_OVC_GMARK,
-       USB31_PWEN_GMARK,
+       USB3_OVC_GMARK,
+       USB3_PWEN_GMARK,
        USB30_OVC_GMARK,
        USB30_PWEN_GMARK,
        USB1_OVC_GMARK,
@@ -1347,8 +1423,8 @@ enum {
        SSI_SDATA2_A_GMARK,
        SSI_SDATA1_A_GMARK,
        SSI_SDATA0_GMARK,
-       SSI_WS0129_GMARK,
-       SSI_SCK0129_GMARK,
+       SSI_WS01239_GMARK,
+       SSI_SCK01239_GMARK,
 
        /* GPSR7 */
        HDMI1_CEC_MARK,
@@ -1360,7 +1436,7 @@ enum {
        AVB_MDC_IMARK,
        MSIOF2_SS2_C_MARK,
        AVB_MAGIC_IMARK,
-       MSIOF2_S1_C_MARK,
+       MSIOF2_SS1_C_MARK,
        SCK4_A_MARK,
        AVB_PHY_INT_IMARK,
        MSIOF2_SYNC_C_MARK,
@@ -1371,6 +1447,7 @@ enum {
        AVB_AVTP_MATCH_A_IMARK,
        MSIOF2_RXD_C_MARK,
        CTS4x_A_MARK,
+       FSCLKST2x_A_MARK,
        AVB_AVTP_CAPTURE_A_IMARK,
        MSIOF2_TXD_C_MARK,
        RTS4x_TANS_A_MARK,
@@ -1380,50 +1457,51 @@ enum {
        VI4_DATA0_B_MARK,
        CAN0_TX_B_MARK,
        CANFD0_TX_B_MARK,
+       MSIOF3_SS2_E_MARK,
        IRQ1_IMARK,
        QPOLA_MARK,
        DU_DISP_MARK,
        VI4_DATA1_B_MARK,
        CAN0_RX_B_MARK,
        CANFD0_RX_B_MARK,
+       MSIOF3_SS1_E_MARK,
 
        /* IPSR1 */
        IRQ2_IMARK,
        QCPV_QDE_MARK,
        DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
        VI4_DATA2_B_MARK,
+       MSIOF3_SYNC_E_MARK,
        PWM3_B_MARK,
        IRQ3_IMARK,
        QSTVB_QVE_MARK,
-       A25_MARK,
        DU_DOTCLKOUT1_MARK,
        VI4_DATA3_B_MARK,
+       MSIOF3_SCK_E_MARK,
        PWM4_B_MARK,
        IRQ4_IMARK,
        QSTH_QHS_MARK,
-       A24_MARK,
        DU_EXHSYNC_DU_HSYNC_MARK,
        VI4_DATA4_B_MARK,
+       MSIOF3_RXD_E_MARK,
        PWM5_B_MARK,
        IRQ5_IMARK,
        QSTB_QHE_MARK,
-       A23_MARK,
        DU_EXVSYNC_DU_VSYNC_MARK,
        VI4_DATA5_B_MARK,
+       FSCLKST2x_B_MARK,
+       MSIOF3_TXD_E_MARK,
        PWM6_B_MARK,
        PWM0_IMARK,
        AVB_AVTP_PPS_MARK,
-       A22_MARK,
        VI4_DATA6_B_MARK,
        IECLK_B_MARK,
        PWM1_A_IMARK,
-       A21_MARK,
        HRX3_D_MARK,
        VI4_DATA7_B_MARK,
        IERX_B_MARK,
        PWM2_A_IMARK,
        PWMFSW0_MARK,
-       A20_MARK,
        HTX3_D_MARK,
        IETX_B_MARK,
        A0_IMARK,
@@ -1505,7 +1583,6 @@ enum {
        SCL6_A_MARK,
        AVB_AVTP_CAPTURE_B_MARK,
        PWM2_B_MARK,
-       SPV_EVEN_MARK,
        A12_IMARK,
        LCDOUT12_MARK,
        MSIOF3_SCK_C_MARK,
@@ -1711,67 +1788,94 @@ enum {
        SD1_CLK_IMARK,
        MSIOF1_SCK_G_MARK,
        SIM0_CLK_A_MARK,
-
        SD1_CMD_IMARK,
        MSIOF1_SYNC_G_MARK,
+       NFCEx_B_MARK,
        SIM0_D_A_MARK,
        STP_IVCXO27_1_B_MARK,
-
        SD1_DAT0_IMARK,
        SD2_DAT4_MARK,
        MSIOF1_RXD_G_MARK,
+       NFWPx_B_MARK,
        TS_SCK1_B_MARK,
        STP_ISCLK_1_B_MARK,
-
        SD1_DAT1_IMARK,
        SD2_DAT5_MARK,
        MSIOF1_TXD_G_MARK,
+       NFDATA14_B_MARK,
        TS_SPSYNC1_B_MARK,
        STP_ISSYNC_1_B_MARK,
-
        SD1_DAT2_IMARK,
        SD2_DAT6_MARK,
        MSIOF1_SS1_G_MARK,
+       NFDATA15_B_MARK,
        TS_SDAT1_B_MARK,
        STP_IOD_1_B_MARK,
        SD1_DAT3_IMARK,
        SD2_DAT7_MARK,
        MSIOF1_SS2_G_MARK,
+       NFRBx_B_MARK,
        TS_SDEN1_B_MARK,
        STP_ISEN_1_B_MARK,
 
        /* IPSR9 */
        SD2_CLK_IMARK,
-       SCKZ_A_MARK,
+       NFDATA8_MARK,
+       SD2_CMD_IMARK,
+       NFDATA9_MARK,
        SD2_DAT0_IMARK,
-       MTSx_A_MARK,
+       NFDATA10_MARK,
        SD2_DAT1_IMARK,
-       STMx_A_MARK,
+       NFDATA11_MARK,
        SD2_DAT2_IMARK,
-       MDATA_A_MARK,
+       NFDATA12_MARK,
        SD2_DAT3_IMARK,
-       SDATA_A_MARK,
+       NFDATA13_MARK,
        SD2_DS_IMARK,
+       NFALE_MARK,
        SATA_DEVSLP_B_MARK,
-       VSP_A_MARK,
+       SD3_CLK_IMARK,
+       NFWEx_MARK,
+
+       /* IPSR10 */
+       SD3_CMD_IMARK,
+       NFREx_MARK,
+       SD3_DAT0_IMARK,
+       NFDATA0_MARK,
+       SD3_DAT1_IMARK,
+       NFDATA1_MARK,
+       SD3_DAT2_IMARK,
+       NFDATA2_MARK,
+       SD3_DAT3_IMARK,
+       NFDATA3_MARK,
        SD3_DAT4_IMARK,
        SD2_CD_A_MARK,
+       NFDATA4_MARK,
        SD3_DAT5_IMARK,
        SD2_WP_A_MARK,
-
-       /* IPSR10 */
+       NFDATA5_MARK,
        SD3_DAT6_IMARK,
        SD3_CD_MARK,
+       NFDATA6_MARK,
+
+       /* IPSR11 */
        SD3_DAT7_IMARK,
        SD3_WP_MARK,
+       NFDATA7_MARK,
+       SD3_DS_IMARK,
+       NFCLE_MARK,
        SD0_CD_IMARK,
+       NFDATA14_A_MARK,
        SCL2_B_MARK,
        SIM0_RST_A_MARK,
        SD0_WP_IMARK,
+       NFDATA15_A_MARK,
        SDA2_B_MARK,
        SD1_CD_IMARK,
+       NFRBx_A_MARK,
        SIM0_CLK_B_MARK,
        SD1_WP_IMARK,
+       NFCEx_A_MARK,
        SIM0_D_B_MARK,
        SCK0_IMARK,
        HSCK1_B_MARK,
@@ -1779,16 +1883,17 @@ enum {
        AUDIO_CLKC_B_MARK,
        SDA2_A_MARK,
        SIM0_RST_B_MARK,
-       STP_OPWM__C_MARK,
+       STP_OPWM_0_C_MARK,
        RIF0_CLK_B_MARK,
        ADICHS2_MARK,
+       SCK5_B_MARK,
        RX0_IMARK,
        HRX1_B_MARK,
        TS_SCK0_C_MARK,
        STP_ISCLK_0_C_MARK,
        RIF0_D0_B_MARK,
 
-       /* IPSR11 */
+       /* IPSR12 */
        TX0_IMARK,
        HTX1_B_MARK,
        TS_SPSYNC0_C_MARK,
@@ -1813,7 +1918,7 @@ enum {
        RX1_A_IMARK,
        HRX1_A_MARK,
        TS_SDAT0_C_MARK,
-       STP_IDS_0_C_MARK,
+       STP_ISD_0_C_MARK,
        RIF1_CLK_C_MARK,
        TX1_A_IMARK,
        HTX1_A_MARK,
@@ -1842,21 +1947,19 @@ enum {
        RIF1_CLK_B_MARK,
        ADICLK_MARK,
 
-       /* IPSR12 */
+       /* IPSR13 */
        TX2_A_IMARK,
        SD2_CD_B_MARK,
        SCL1_A_MARK,
-       RSD_CLK_B_MARK,
        FMCLK_A_MARK,
        RIF1_D1_C_MARK,
-       FSO_CFE_0_B_MARK,
+       FSO_CFE_0x_MARK,
        RX2_A_IMARK,
        SD2_WP_B_MARK,
        SDA1_A_MARK,
-       RDS_DATA_B_MARK,
-       RMIN_A_MARK,
+       FMIN_A_MARK,
        RIF1_SYNC_C_MARK,
-       FSO_CEF_1_B_MARK,
+       FSO_CFE_1x_MARK,
        HSCK0_IMARK,
        MSIOF1_SCK_D_MARK,
        AUDIO_CLKB_A_MARK,
@@ -1864,21 +1967,19 @@ enum {
        TS_SCK0_D_MARK,
        STP_ISCLK_0_D_MARK,
        RIF0_CLK_C_MARK,
-       AD_CLK_MARK,
+       RX5_B_MARK,
        HRX0_IMARK,
        MSIOF1_RXD_D_MARK,
-       SS1_SDATA2_B_MARK,
+       SSI_SDATA2_B_MARK,
        TS_SDEN0_D_MARK,
        STP_ISEN_0_D_MARK,
        RIF0_D0_C_MARK,
-       AD_DI_MARK,
        HTX0_IMARK,
        MSIOF1_TXD_D_MARK,
        SSI_SDATA9_B_MARK,
        TS_SDAT0_D_MARK,
        STP_ISD_0_D_MARK,
        RIF0_D1_C_MARK,
-       AD_DO_MARK,
        HCTS0x_IMARK,
        RX2_B_MARK,
        MSIOF1_SYNC_D_MARK,
@@ -1887,7 +1988,6 @@ enum {
        STP_ISSYNC_0_D_MARK,
        RIF0_SYNC_C_MARK,
        AUDIO_CLKOUT1_A_MARK,
-       AD_NSCx_MARK,
        HRTS0x_IMARK,
        TX2_B_MARK,
        MSIOF1_SS1_D_MARK,
@@ -1897,22 +1997,23 @@ enum {
        AUDIO_CLKOUT2_A_MARK,
        MSIOF0_SYNC_IMARK,
        AUDIO_CLKOUT_A_MARK,
+       TX5_B_MARK,
+       BPFCLK_D_MARK,
 
-       /* IPSR13 */
+       /* IPSR14 */
        MSIOF0_SS1_IMARK,
-       RX5_MARK,
+       RX5_A_MARK,
+       NFWPx_A_MARK,
        AUDIO_CLKA_C_MARK,
        SSI_SCK2_A_MARK,
-       RDS_CLK_A_MARK,
        STP_IVCXO27_0_C_MARK,
        AUDIO_CLKOUT3_A_MARK,
        TCLK1_B_MARK,
        MSIOF0_SS2_IMARK,
-       TX5_MARK,
+       TX5_A_MARK,
        MSIOF1_SS2_D_MARK,
        AUDIO_CLKC_A_MARK,
        SSI_WS2_A_MARK,
-       RDS_DATA_A_MARK,
        STP_OPWM_0_D_MARK,
        AUDIO_CLKOUT_D_MARK,
        SPEEDIN_B_MARK,
@@ -1926,17 +2027,17 @@ enum {
        MLB_DAT_IMARK,
        TX1_B_MARK,
        MSIOF1_RXD_F_MARK,
-       SSI_SCK0129_IMARK,
+       SSI_SCK01239_IMARK,
        MSIOF1_TXD_F_MARK,
        MOUT0_MARK,
-       SSI_WS0129_IMARK,
+       SSI_WS01239_IMARK,
        MSIOF1_SS1_F_MARK,
        MOUT1_MARK,
        SSI_SDATA0_IMARK,
        MSIOF1_SS2_F_MARK,
        MOUT2_MARK,
 
-       /* IPSR14 */
+       /* IPSR15 */
        SSI_SDATA1_A_IMARK,
        MOUT5_MARK,
        SSI_SDATA2_A_IMARK,
@@ -1978,16 +2079,13 @@ enum {
        RIF0_D0_A_MARK,
        RIF2_D1_A_MARK,
 
+       /* IPSR16 */
        SSI_SCK6_IMARK,
-       USB2_PWEN_MARK,
        SIM0_RST_D_MARK,
-       RDS_CLK_C_MARK,
        SSI_WS6_IMARK,
-       USB2_OVC_MARK,
        SIM0_D_D_MARK,
        SSI_SDATA6_IMARK,
        SIM0_CLK_D_MARK,
-       RSD_DATA_C_MARK,
        SATA_DEVSLP_A_MARK,
        SSI_SCK78_IMARK,
        HRX2_B_MARK,
@@ -1999,7 +2097,7 @@ enum {
        SSI_WS78_IMARK,
        HTX2_B_MARK,
        MSIOF1_SYNC_C_MARK,
-       TS_SDT1_A_MARK,
+       TS_SDAT1_A_MARK,
        STP_ISD_1_A_MARK,
        RIF1_SYNC_A_MARK,
        RIF3_SYNC_A_MARK,
@@ -2007,7 +2105,7 @@ enum {
        HCTS2x_B_MARK,
        MSIOF1_RXD_C_MARK,
        TS_SDEN1_A_MARK,
-       STP_IEN_1_A_MARK,
+       STP_ISEN_1_A_MARK,
        RIF1_D0_A_MARK,
        RIF3_D0_A_MARK,
        TCLK2_A_MARK,
@@ -2017,7 +2115,7 @@ enum {
        TS_SPSYNC1_A_MARK,
        STP_ISSYNC_1_A_MARK,
        RIF1_D1_A_MARK,
-       EIF3_D1_A_MARK,
+       RIF3_D1_A_MARK,
        SSI_SDATA9_A_IMARK,
        HSCK2_B_MARK,
        MSIOF1_SS1_C_MARK,
@@ -2025,31 +2123,29 @@ enum {
        SSI_WS1_B_MARK,
        SCK1_MARK,
        STP_IVCXO27_1_A_MARK,
-       SCK5_MARK,
+       SCK5_A_MARK,
 
-       /* IPSR16 */
+       /* IPSR17 */
        AUDIO_CLKA_A_IMARK,
        CC5_OSCOUT_MARK,
        AUDIO_CLKB_B_IMARK,
        SCIF_CLK_A_MARK,
-       DVC_MUTE_MARK,
        STP_IVCXO27_1_D_MARK,
        REMOCON_A_MARK,
        TCLK1_A_MARK,
-       VSP_B_MARK,
        USB0_PWEN_IMARK,
        SIM0_RST_C_MARK,
        TS_SCK1_D_MARK,
        STP_ISCLK_1_D_MARK,
        BPFCLK_B_MARK,
        RIF3_CLK_B_MARK,
-       SCKZ_B_MARK,
+       HSCK2_C_MARK,
        USB0_OVC_IMARK,
        SIM0_D_C_MARK,
        TS_SDAT1_D_MARK,
        STP_ISD_1_D_MARK,
        RIF3_SYNC_B_MARK,
-       VSP_C_MARK,
+       HRX2_C_MARK,
        USB1_PWEN_IMARK,
        SIM0_CLK_C_MARK,
        SSI_SCK1_A_MARK,
@@ -2057,9 +2153,8 @@ enum {
        STP_ISCLK_0_E_MARK,
        FMCLK_B_MARK,
        RIF2_CLK_B_MARK,
-       MTSx_B_MARK,
        SPEEDIN_A_MARK,
-       VSP_D_MARK,
+       HTX2_C_MARK,
        USB1_OVC_IMARK,
        MSIOF1_SS2_C_MARK,
        SSI_WS1_A_MARK,
@@ -2067,8 +2162,8 @@ enum {
        STP_ISD_0_E_MARK,
        FMIN_B_MARK,
        RIF2_SYNC_B_MARK,
-       STMx_B_MARK,
        REMOCON_B_MARK,
+       HCTS2x_C_MARK,
        USB30_PWEN_IMARK,
        AUDIO_CLKOUT_B_MARK,
        SSI_SCK2_B_MARK,
@@ -2076,9 +2171,10 @@ enum {
        STP_ISEN_1_D_MARK,
        STP_OPWM_0_E_MARK,
        RIF3_D0_B_MARK,
-       MDATA_B_MARK,
        TCLK2_B_MARK,
        TPU0TO0_MARK,
+       BPFCLK_C_MARK,
+       HRTS2x_C_MARK,
        USB30_OVC_IMARK,
        AUDIO_CLKOUT1_B_MARK,
        SSI_WS2_B_MARK,
@@ -2086,26 +2182,9 @@ enum {
        STP_ISSYNC_1_D_MARK,
        STP_IVCXO27_0_E_MARK,
        RIF3_D1_B_MARK,
-       SDATA_B_MARK,
-       RSO_TOE_B_MARK,
+       FSO_TOEx_MARK,
        TPU0TO1_MARK,
 
-       /* IPSR17 */
-       USB31_PWEN_IMARK,
-       AUDIO_CLKOUT2_B_MARK,
-       SI_SCK9_B_MARK,
-       TS_SDEN0_E_MARK,
-       STP_ISEN_0_E_MARK,
-       RIF2_D0_B_MARK,
-       TPU0TO2_MARK,
-       USB31_OVC_IMARK,
-       AUDIO_CLKOUT3_B_MARK,
-       SSI_WS9_B_MARK,
-       TS_SPSYNC0_E_MARK,
-       STP_ISSYNC_0_E_MARK,
-       RIF2_D1_B_MARK,
-       TPU0TO3_MARK,
-
        PINMUX_MARK_END,
 };
 
@@ -2131,6 +2210,7 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(D0_GMARK, GFN_D0),
 
        /* GPSR1 */
+       PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT),
        PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),
        PINMUX_DATA(WE1x_GMARK, GFN_WE1x),
        PINMUX_DATA(WE0x_GMARK, GFN_WE0x),
@@ -2196,23 +2276,23 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),
 
        /* GPSR4 */
-       PINMUX_DATA(SD3_DS_MARK, FN_SD3_DS),
+       PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS),
        PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),
        PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),
        PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),
        PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),
-       PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3),
-       PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2),
-       PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1),
-       PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0),
-       PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD),
-       PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK),
+       PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3),
+       PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2),
+       PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1),
+       PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0),
+       PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD),
+       PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK),
        PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),
        PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),
        PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),
        PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),
        PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),
-       PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD),
+       PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD),
        PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),
 
        /* GPSR5 */
@@ -2244,8 +2324,8 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(SCK0_GMARK, GFN_SCK0),
 
        /* GPSR6 */
-       PINMUX_DATA(USB31_OVC_GMARK, GFN_USB31_OVC),
-       PINMUX_DATA(USB31_PWEN_GMARK, GFN_USB31_PWEN),
+       PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC),
+       PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN),
        PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),
        PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),
        PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),
@@ -2274,16 +2354,14 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),
        PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),
        PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),
-       PINMUX_DATA(SSI_WS0129_GMARK, GFN_SSI_WS0129),
-       PINMUX_DATA(SSI_SCK0129_GMARK, GFN_SSI_SCK0129),
+       PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239),
+       PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239),
 
        /* GPSR7 */
        PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),
        PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),
        PINMUX_DATA(AVS2_MARK, FN_AVS2),
        PINMUX_DATA(AVS1_MARK, FN_AVS1),
-
-       /* ipsr setting .. underconstruction */
 };
 
 static struct pinmux_gpio pinmux_gpios[] = {
@@ -2306,6 +2384,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_GFN(D1),
        GPIO_GFN(D0),
        /* GPSR1 */
+       GPIO_GFN(CLKOUT),
        GPIO_GFN(EX_WAIT0_A),
        GPIO_GFN(WE1x),
        GPIO_GFN(WE0x),
@@ -2371,23 +2450,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_GFN(SD0_CLK),
 
        /* GPSR4 */
-       GPIO_FN(SD3_DS),
+       GPIO_GFN(SD3_DS),
        GPIO_GFN(SD3_DAT7),
        GPIO_GFN(SD3_DAT6),
        GPIO_GFN(SD3_DAT5),
        GPIO_GFN(SD3_DAT4),
-       GPIO_FN(SD3_DAT3),
-       GPIO_FN(SD3_DAT2),
-       GPIO_FN(SD3_DAT1),
-       GPIO_FN(SD3_DAT0),
-       GPIO_FN(SD3_CMD),
-       GPIO_FN(SD3_CLK),
+       GPIO_GFN(SD3_DAT3),
+       GPIO_GFN(SD3_DAT2),
+       GPIO_GFN(SD3_DAT1),
+       GPIO_GFN(SD3_DAT0),
+       GPIO_GFN(SD3_CMD),
+       GPIO_GFN(SD3_CLK),
        GPIO_GFN(SD2_DS),
        GPIO_GFN(SD2_DAT3),
        GPIO_GFN(SD2_DAT2),
        GPIO_GFN(SD2_DAT1),
        GPIO_GFN(SD2_DAT0),
-       GPIO_FN(SD2_CMD),
+       GPIO_GFN(SD2_CMD),
        GPIO_GFN(SD2_CLK),
 
        /* GPSR5 */
@@ -2419,8 +2498,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_GFN(SCK0),
 
        /* GPSR6 */
-       GPIO_GFN(USB31_OVC),
-       GPIO_GFN(USB31_PWEN),
+       GPIO_GFN(USB3_OVC),
+       GPIO_GFN(USB3_PWEN),
        GPIO_GFN(USB30_OVC),
        GPIO_GFN(USB30_PWEN),
        GPIO_GFN(USB1_OVC),
@@ -2449,8 +2528,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_GFN(SSI_SDATA2_A),
        GPIO_GFN(SSI_SDATA1_A),
        GPIO_GFN(SSI_SDATA0),
-       GPIO_GFN(SSI_WS0129),
-       GPIO_GFN(SSI_SCK0129),
+       GPIO_GFN(SSI_WS01239),
+       GPIO_GFN(SSI_SCK01239),
 
        /* GPSR7 */
        GPIO_FN(HDMI1_CEC),
@@ -2462,7 +2541,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(AVB_MDC),
        GPIO_FN(MSIOF2_SS2_C),
        GPIO_IFN(AVB_MAGIC),
-       GPIO_FN(MSIOF2_S1_C),
+       GPIO_FN(MSIOF2_SS1_C),
        GPIO_FN(SCK4_A),
        GPIO_IFN(AVB_PHY_INT),
        GPIO_FN(MSIOF2_SYNC_C),
@@ -2473,6 +2552,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(AVB_AVTP_MATCH_A),
        GPIO_FN(MSIOF2_RXD_C),
        GPIO_FN(CTS4x_A),
+       GPIO_FN(FSCLKST2x_A),
        GPIO_IFN(AVB_AVTP_CAPTURE_A),
        GPIO_FN(MSIOF2_TXD_C),
        GPIO_FN(RTS4x_TANS_A),
@@ -2482,50 +2562,50 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(VI4_DATA0_B),
        GPIO_FN(CAN0_TX_B),
        GPIO_FN(CANFD0_TX_B),
+       GPIO_FN(MSIOF3_SS2_E),
        GPIO_IFN(IRQ1),
        GPIO_FN(QPOLA),
        GPIO_FN(DU_DISP),
        GPIO_FN(VI4_DATA1_B),
        GPIO_FN(CAN0_RX_B),
        GPIO_FN(CANFD0_RX_B),
+       GPIO_FN(MSIOF3_SS1_E),
 
        /* IPSR1 */
        GPIO_IFN(IRQ2),
        GPIO_FN(QCPV_QDE),
        GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),
        GPIO_FN(VI4_DATA2_B),
+       GPIO_FN(MSIOF3_SYNC_E),
        GPIO_FN(PWM3_B),
        GPIO_IFN(IRQ3),
        GPIO_FN(QSTVB_QVE),
-       GPIO_FN(A25),
        GPIO_FN(DU_DOTCLKOUT1),
        GPIO_FN(VI4_DATA3_B),
+       GPIO_FN(MSIOF3_SCK_E),
        GPIO_FN(PWM4_B),
        GPIO_IFN(IRQ4),
        GPIO_FN(QSTH_QHS),
-       GPIO_FN(A24),
        GPIO_FN(DU_EXHSYNC_DU_HSYNC),
        GPIO_FN(VI4_DATA4_B),
+       GPIO_FN(MSIOF3_RXD_E),
        GPIO_FN(PWM5_B),
        GPIO_IFN(IRQ5),
        GPIO_FN(QSTB_QHE),
-       GPIO_FN(A23),
        GPIO_FN(DU_EXVSYNC_DU_VSYNC),
        GPIO_FN(VI4_DATA5_B),
+       GPIO_FN(FSCLKST2x_B),
+       GPIO_FN(MSIOF3_TXD_E),
        GPIO_FN(PWM6_B),
        GPIO_IFN(PWM0),
        GPIO_FN(AVB_AVTP_PPS),
-       GPIO_FN(A22),
        GPIO_FN(VI4_DATA6_B),
        GPIO_FN(IECLK_B),
        GPIO_IFN(PWM1_A),
-       GPIO_FN(A21),
        GPIO_FN(HRX3_D),
        GPIO_FN(VI4_DATA7_B),
        GPIO_FN(IERX_B),
        GPIO_IFN(PWM2_A),
-       GPIO_FN(PWMFSW0),
-       GPIO_FN(A20),
        GPIO_FN(HTX3_D),
        GPIO_FN(IETX_B),
        GPIO_IFN(A0),
@@ -2607,7 +2687,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(SCL6_A),
        GPIO_FN(AVB_AVTP_CAPTURE_B),
        GPIO_FN(PWM2_B),
-       GPIO_FN(SPV_EVEN),
        GPIO_IFN(A12),
        GPIO_FN(LCDOUT12),
        GPIO_FN(MSIOF3_SCK_C),
@@ -2813,67 +2892,94 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(SD1_CLK),
        GPIO_FN(MSIOF1_SCK_G),
        GPIO_FN(SIM0_CLK_A),
-
        GPIO_IFN(SD1_CMD),
        GPIO_FN(MSIOF1_SYNC_G),
+       GPIO_FN(NFCEx_B),
        GPIO_FN(SIM0_D_A),
        GPIO_FN(STP_IVCXO27_1_B),
-
        GPIO_IFN(SD1_DAT0),
        GPIO_FN(SD2_DAT4),
        GPIO_FN(MSIOF1_RXD_G),
+       GPIO_FN(NFWPx_B),
        GPIO_FN(TS_SCK1_B),
        GPIO_FN(STP_ISCLK_1_B),
-
        GPIO_IFN(SD1_DAT1),
        GPIO_FN(SD2_DAT5),
        GPIO_FN(MSIOF1_TXD_G),
+       GPIO_FN(NFDATA14_B),
        GPIO_FN(TS_SPSYNC1_B),
        GPIO_FN(STP_ISSYNC_1_B),
-
        GPIO_IFN(SD1_DAT2),
        GPIO_FN(SD2_DAT6),
        GPIO_FN(MSIOF1_SS1_G),
+       GPIO_FN(NFDATA15_B),
        GPIO_FN(TS_SDAT1_B),
        GPIO_FN(STP_IOD_1_B),
        GPIO_IFN(SD1_DAT3),
        GPIO_FN(SD2_DAT7),
        GPIO_FN(MSIOF1_SS2_G),
+       GPIO_FN(NFRBx_B),
        GPIO_FN(TS_SDEN1_B),
        GPIO_FN(STP_ISEN_1_B),
 
        /* IPSR9 */
        GPIO_IFN(SD2_CLK),
-       GPIO_FN(SCKZ_A),
+       GPIO_FN(NFDATA8),
+       GPIO_IFN(SD2_CMD),
+       GPIO_FN(NFDATA9),
        GPIO_IFN(SD2_DAT0),
-       GPIO_FN(MTSx_A),
+       GPIO_FN(NFDATA10),
        GPIO_IFN(SD2_DAT1),
-       GPIO_FN(STMx_A),
+       GPIO_FN(NFDATA11),
        GPIO_IFN(SD2_DAT2),
-       GPIO_FN(MDATA_A),
+       GPIO_FN(NFDATA12),
        GPIO_IFN(SD2_DAT3),
-       GPIO_FN(SDATA_A),
+       GPIO_FN(NFDATA13),
        GPIO_IFN(SD2_DS),
+       GPIO_FN(NFALE),
        GPIO_FN(SATA_DEVSLP_B),
-       GPIO_FN(VSP_A),
+       GPIO_IFN(SD3_CLK),
+       GPIO_FN(NFWEx),
+
+       /* IPSR10 */
+       GPIO_IFN(SD3_CMD),
+       GPIO_FN(NFREx),
+       GPIO_IFN(SD3_DAT0),
+       GPIO_FN(NFDATA0),
+       GPIO_IFN(SD3_DAT1),
+       GPIO_FN(NFDATA1),
+       GPIO_IFN(SD3_DAT2),
+       GPIO_FN(NFDATA2),
+       GPIO_IFN(SD3_DAT3),
+       GPIO_FN(NFDATA3),
        GPIO_IFN(SD3_DAT4),
        GPIO_FN(SD2_CD_A),
+       GPIO_FN(NFDATA4),
        GPIO_IFN(SD3_DAT5),
        GPIO_FN(SD2_WP_A),
-
-       /* IPSR10 */
+       GPIO_FN(NFDATA5),
        GPIO_IFN(SD3_DAT6),
        GPIO_FN(SD3_CD),
+       GPIO_FN(NFDATA6),
+
+       /* IPSR11 */
        GPIO_IFN(SD3_DAT7),
        GPIO_FN(SD3_WP),
+       GPIO_FN(NFDATA7),
+       GPIO_IFN(SD3_DS),
+       GPIO_FN(NFCLE),
        GPIO_IFN(SD0_CD),
+       GPIO_FN(NFDATA14_A),
        GPIO_FN(SCL2_B),
        GPIO_FN(SIM0_RST_A),
        GPIO_IFN(SD0_WP),
+       GPIO_FN(NFDATA15_A),
        GPIO_FN(SDA2_B),
        GPIO_IFN(SD1_CD),
+       GPIO_FN(NFRBx_A),
        GPIO_FN(SIM0_CLK_B),
        GPIO_IFN(SD1_WP),
+       GPIO_FN(NFCEx_A),
        GPIO_FN(SIM0_D_B),
        GPIO_IFN(SCK0),
        GPIO_FN(HSCK1_B),
@@ -2881,16 +2987,17 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(AUDIO_CLKC_B),
        GPIO_FN(SDA2_A),
        GPIO_FN(SIM0_RST_B),
-       GPIO_FN(STP_OPWM__C),
+       GPIO_FN(STP_OPWM_0_C),
        GPIO_FN(RIF0_CLK_B),
        GPIO_FN(ADICHS2),
+       GPIO_FN(SCK5_B),
        GPIO_IFN(RX0),
        GPIO_FN(HRX1_B),
        GPIO_FN(TS_SCK0_C),
        GPIO_FN(STP_ISCLK_0_C),
        GPIO_FN(RIF0_D0_B),
 
-       /* IPSR11 */
+       /* IPSR12 */
        GPIO_IFN(TX0),
        GPIO_FN(HTX1_B),
        GPIO_FN(TS_SPSYNC0_C),
@@ -2915,7 +3022,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(RX1_A),
        GPIO_FN(HRX1_A),
        GPIO_FN(TS_SDAT0_C),
-       GPIO_FN(STP_IDS_0_C),
+       GPIO_FN(STP_ISD_0_C),
        GPIO_FN(RIF1_CLK_C),
        GPIO_IFN(TX1_A),
        GPIO_FN(HTX1_A),
@@ -2944,21 +3051,19 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(RIF1_CLK_B),
        GPIO_FN(ADICLK),
 
-       /* IPSR12 */
+       /* IPSR13 */
        GPIO_IFN(TX2_A),
        GPIO_FN(SD2_CD_B),
        GPIO_FN(SCL1_A),
-       GPIO_FN(RSD_CLK_B),
        GPIO_FN(FMCLK_A),
        GPIO_FN(RIF1_D1_C),
-       GPIO_FN(FSO_CFE_0_B),
+       GPIO_FN(FSO_CFE_0x),
        GPIO_IFN(RX2_A),
        GPIO_FN(SD2_WP_B),
        GPIO_FN(SDA1_A),
-       GPIO_FN(RDS_DATA_B),
-       GPIO_FN(RMIN_A),
+       GPIO_FN(FMIN_A),
        GPIO_FN(RIF1_SYNC_C),
-       GPIO_FN(FSO_CEF_1_B),
+       GPIO_FN(FSO_CFE_1x),
        GPIO_IFN(HSCK0),
        GPIO_FN(MSIOF1_SCK_D),
        GPIO_FN(AUDIO_CLKB_A),
@@ -2966,21 +3071,19 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(TS_SCK0_D),
        GPIO_FN(STP_ISCLK_0_D),
        GPIO_FN(RIF0_CLK_C),
-       GPIO_FN(AD_CLK),
+       GPIO_FN(RX5_B),
        GPIO_IFN(HRX0),
        GPIO_FN(MSIOF1_RXD_D),
-       GPIO_FN(SS1_SDATA2_B),
+       GPIO_FN(SSI_SDATA2_B),
        GPIO_FN(TS_SDEN0_D),
        GPIO_FN(STP_ISEN_0_D),
        GPIO_FN(RIF0_D0_C),
-       GPIO_FN(AD_DI),
        GPIO_IFN(HTX0),
        GPIO_FN(MSIOF1_TXD_D),
        GPIO_FN(SSI_SDATA9_B),
        GPIO_FN(TS_SDAT0_D),
        GPIO_FN(STP_ISD_0_D),
        GPIO_FN(RIF0_D1_C),
-       GPIO_FN(AD_DO),
        GPIO_IFN(HCTS0x),
        GPIO_FN(RX2_B),
        GPIO_FN(MSIOF1_SYNC_D),
@@ -2989,7 +3092,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(STP_ISSYNC_0_D),
        GPIO_FN(RIF0_SYNC_C),
        GPIO_FN(AUDIO_CLKOUT1_A),
-       GPIO_FN(AD_NSCx),
        GPIO_IFN(HRTS0x),
        GPIO_FN(TX2_B),
        GPIO_FN(MSIOF1_SS1_D),
@@ -2999,22 +3101,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(AUDIO_CLKOUT2_A),
        GPIO_IFN(MSIOF0_SYNC),
        GPIO_FN(AUDIO_CLKOUT_A),
+       GPIO_FN(TX5_B),
+       GPIO_FN(BPFCLK_D),
 
-       /* IPSR13 */
+       /* IPSR14 */
        GPIO_IFN(MSIOF0_SS1),
-       GPIO_FN(RX5),
+       GPIO_FN(RX5_A),
+       GPIO_FN(NFWPx_A),
        GPIO_FN(AUDIO_CLKA_C),
        GPIO_FN(SSI_SCK2_A),
-       GPIO_FN(RDS_CLK_A),
        GPIO_FN(STP_IVCXO27_0_C),
        GPIO_FN(AUDIO_CLKOUT3_A),
        GPIO_FN(TCLK1_B),
        GPIO_IFN(MSIOF0_SS2),
-       GPIO_FN(TX5),
+       GPIO_FN(TX5_A),
        GPIO_FN(MSIOF1_SS2_D),
        GPIO_FN(AUDIO_CLKC_A),
        GPIO_FN(SSI_WS2_A),
-       GPIO_FN(RDS_DATA_A),
        GPIO_FN(STP_OPWM_0_D),
        GPIO_FN(AUDIO_CLKOUT_D),
        GPIO_FN(SPEEDIN_B),
@@ -3028,17 +3131,17 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(MLB_DAT),
        GPIO_FN(TX1_B),
        GPIO_FN(MSIOF1_RXD_F),
-       GPIO_IFN(SSI_SCK0129),
+       GPIO_IFN(SSI_SCK01239),
        GPIO_FN(MSIOF1_TXD_F),
        GPIO_FN(MOUT0),
-       GPIO_IFN(SSI_WS0129),
+       GPIO_IFN(SSI_WS01239),
        GPIO_FN(MSIOF1_SS1_F),
        GPIO_FN(MOUT1),
        GPIO_IFN(SSI_SDATA0),
        GPIO_FN(MSIOF1_SS2_F),
        GPIO_FN(MOUT2),
 
-       /* IPSR14 */
+       /* IPSR15 */
        GPIO_IFN(SSI_SDATA1_A),
        GPIO_FN(MOUT5),
        GPIO_IFN(SSI_SDATA2_A),
@@ -3080,16 +3183,13 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(RIF0_D0_A),
        GPIO_FN(RIF2_D1_A),
 
+       /* IPSR16 */
        GPIO_IFN(SSI_SCK6),
-       GPIO_FN(USB2_PWEN),
        GPIO_FN(SIM0_RST_D),
-       GPIO_FN(RDS_CLK_C),
        GPIO_IFN(SSI_WS6),
-       GPIO_FN(USB2_OVC),
        GPIO_FN(SIM0_D_D),
        GPIO_IFN(SSI_SDATA6),
        GPIO_FN(SIM0_CLK_D),
-       GPIO_FN(RSD_DATA_C),
        GPIO_FN(SATA_DEVSLP_A),
        GPIO_IFN(SSI_SCK78),
        GPIO_FN(HRX2_B),
@@ -3101,7 +3201,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_IFN(SSI_WS78),
        GPIO_FN(HTX2_B),
        GPIO_FN(MSIOF1_SYNC_C),
-       GPIO_FN(TS_SDT1_A),
+       GPIO_FN(TS_SDAT1_A),
        GPIO_FN(STP_ISD_1_A),
        GPIO_FN(RIF1_SYNC_A),
        GPIO_FN(RIF3_SYNC_A),
@@ -3109,7 +3209,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(HCTS2x_B),
        GPIO_FN(MSIOF1_RXD_C),
        GPIO_FN(TS_SDEN1_A),
-       GPIO_FN(STP_IEN_1_A),
+       GPIO_FN(STP_ISEN_1_A),
        GPIO_FN(RIF1_D0_A),
        GPIO_FN(RIF3_D0_A),
        GPIO_FN(TCLK2_A),
@@ -3119,7 +3219,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(TS_SPSYNC1_A),
        GPIO_FN(STP_ISSYNC_1_A),
        GPIO_FN(RIF1_D1_A),
-       GPIO_FN(EIF3_D1_A),
+       GPIO_FN(RIF3_D1_A),
        GPIO_IFN(SSI_SDATA9_A),
        GPIO_FN(HSCK2_B),
        GPIO_FN(MSIOF1_SS1_C),
@@ -3127,31 +3227,29 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(SSI_WS1_B),
        GPIO_FN(SCK1),
        GPIO_FN(STP_IVCXO27_1_A),
-       GPIO_FN(SCK5),
+       GPIO_FN(SCK5_A),
 
-       /* IPSR16 */
+       /* IPSR17 */
        GPIO_IFN(AUDIO_CLKA_A),
        GPIO_FN(CC5_OSCOUT),
        GPIO_IFN(AUDIO_CLKB_B),
        GPIO_FN(SCIF_CLK_A),
-       GPIO_FN(DVC_MUTE),
        GPIO_FN(STP_IVCXO27_1_D),
        GPIO_FN(REMOCON_A),
        GPIO_FN(TCLK1_A),
-       GPIO_FN(VSP_B),
        GPIO_IFN(USB0_PWEN),
        GPIO_FN(SIM0_RST_C),
        GPIO_FN(TS_SCK1_D),
        GPIO_FN(STP_ISCLK_1_D),
        GPIO_FN(BPFCLK_B),
        GPIO_FN(RIF3_CLK_B),
-       GPIO_FN(SCKZ_B),
+       GPIO_FN(HSCK2_C),
        GPIO_IFN(USB0_OVC),
        GPIO_FN(SIM0_D_C),
        GPIO_FN(TS_SDAT1_D),
        GPIO_FN(STP_ISD_1_D),
        GPIO_FN(RIF3_SYNC_B),
-       GPIO_FN(VSP_C),
+       GPIO_FN(HRX2_C),
        GPIO_IFN(USB1_PWEN),
        GPIO_FN(SIM0_CLK_C),
        GPIO_FN(SSI_SCK1_A),
@@ -3159,9 +3257,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(STP_ISCLK_0_E),
        GPIO_FN(FMCLK_B),
        GPIO_FN(RIF2_CLK_B),
-       GPIO_FN(MTSx_B),
        GPIO_FN(SPEEDIN_A),
-       GPIO_FN(VSP_D),
+       GPIO_FN(HTX2_C),
        GPIO_IFN(USB1_OVC),
        GPIO_FN(MSIOF1_SS2_C),
        GPIO_FN(SSI_WS1_A),
@@ -3169,8 +3266,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(STP_ISD_0_E),
        GPIO_FN(FMIN_B),
        GPIO_FN(RIF2_SYNC_B),
-       GPIO_FN(STMx_B),
        GPIO_FN(REMOCON_B),
+       GPIO_FN(HCTS2x_C),
        GPIO_IFN(USB30_PWEN),
        GPIO_FN(AUDIO_CLKOUT_B),
        GPIO_FN(SSI_SCK2_B),
@@ -3178,9 +3275,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(STP_ISEN_1_D),
        GPIO_FN(STP_OPWM_0_E),
        GPIO_FN(RIF3_D0_B),
-       GPIO_FN(MDATA_B),
        GPIO_FN(TCLK2_B),
        GPIO_FN(TPU0TO0),
+       GPIO_FN(BPFCLK_C),
+       GPIO_FN(HRTS2x_C),
        GPIO_IFN(USB30_OVC),
        GPIO_FN(AUDIO_CLKOUT1_B),
        GPIO_FN(SSI_WS2_B),
@@ -3188,25 +3286,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
        GPIO_FN(STP_ISSYNC_1_D),
        GPIO_FN(STP_IVCXO27_0_E),
        GPIO_FN(RIF3_D1_B),
-       GPIO_FN(SDATA_B),
-       GPIO_FN(RSO_TOE_B),
+       GPIO_FN(FSO_TOEx),
        GPIO_FN(TPU0TO1),
-
-       /* IPSR17 */
-       GPIO_IFN(USB31_PWEN),
-       GPIO_FN(AUDIO_CLKOUT2_B),
-       GPIO_FN(SI_SCK9_B),
-       GPIO_FN(TS_SDEN0_E),
-       GPIO_FN(STP_ISEN_0_E),
-       GPIO_FN(RIF2_D0_B),
-       GPIO_FN(TPU0TO2),
-       GPIO_IFN(USB31_OVC),
-       GPIO_FN(AUDIO_CLKOUT3_B),
-       GPIO_FN(SSI_WS9_B),
-       GPIO_FN(TS_SPSYNC0_E),
-       GPIO_FN(STP_ISSYNC_0_E),
-       GPIO_FN(RIF2_D1_B),
-       GPIO_FN(TPU0TO3),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3256,7 +3337,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                0, 0,
                0, 0,
-               0, 0,
+               GP_1_28_FN, GFN_CLKOUT,
                GP_1_27_FN, GFN_EX_WAIT0_A,
                GP_1_26_FN, GFN_WE1x,
                GP_1_25_FN, GFN_WE0x,
@@ -3380,24 +3461,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                0, 0,
                0, 0,
-               GP_4_17_FN, GPIO_FN_SD3_DS,
+               GP_4_17_FN, GFN_SD3_DS,
                GP_4_16_FN, GFN_SD3_DAT7,
 
                GP_4_15_FN, GFN_SD3_DAT6,
                GP_4_14_FN, GFN_SD3_DAT5,
                GP_4_13_FN, GFN_SD3_DAT4,
-               GP_4_12_FN, FN_SD3_DAT3,
-               GP_4_11_FN, FN_SD3_DAT2,
-               GP_4_10_FN, FN_SD3_DAT1,
-               GP_4_9_FN, FN_SD3_DAT0,
-               GP_4_8_FN, FN_SD3_CMD,
-               GP_4_7_FN, FN_SD3_CLK,
+               GP_4_12_FN, GFN_SD3_DAT3,
+               GP_4_11_FN, GFN_SD3_DAT2,
+               GP_4_10_FN, GFN_SD3_DAT1,
+               GP_4_9_FN, GFN_SD3_DAT0,
+               GP_4_8_FN, GFN_SD3_CMD,
+               GP_4_7_FN, GFN_SD3_CLK,
                GP_4_6_FN, GFN_SD2_DS,
                GP_4_5_FN, GFN_SD2_DAT3,
                GP_4_4_FN, GFN_SD2_DAT2,
                GP_4_3_FN, GFN_SD2_DAT1,
                GP_4_2_FN, GFN_SD2_DAT0,
-               GP_4_1_FN, FN_SD2_CMD,
+               GP_4_1_FN, GFN_SD2_CMD,
                GP_4_0_FN, GFN_SD2_CLK }
        },
        /* GPSR5 */
@@ -3410,7 +3491,6 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                GP_5_25_FN, GFN_MLB_DAT,
                GP_5_24_FN, GFN_MLB_SIG,
-
                GP_5_23_FN, GFN_MLB_CLK,
                GP_5_22_FN, FN_MSIOF0_RXD,
                GP_5_21_FN, GFN_MSIOF0_SS2,
@@ -3438,8 +3518,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
        },
        /* GPSR6 */
        { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
-               GP_6_31_FN, GFN_USB31_OVC,
-               GP_6_30_FN, GFN_USB31_PWEN,
+               GP_6_31_FN, GFN_USB3_OVC,
+               GP_6_30_FN, GFN_USB3_PWEN,
                GP_6_29_FN, GFN_USB30_OVC,
                GP_6_28_FN, GFN_USB30_PWEN,
                GP_6_27_FN, GFN_USB1_OVC,
@@ -3468,8 +3548,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_6_4_FN, GFN_SSI_SDATA2_A,
                GP_6_3_FN, GFN_SSI_SDATA1_A,
                GP_6_2_FN, GFN_SSI_SDATA0,
-               GP_6_1_FN, GFN_SSI_WS0129,
-               GP_6_0_FN, GFN_SSI_SCK0129 }
+               GP_6_1_FN, GFN_SSI_WS01239,
+               GP_6_0_FN, GFN_SSI_SCK01239 }
        },
        /* GPSR7 */
        { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
@@ -3513,12 +3593,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                                4, 4, 4, 4, 4, 4, 4, 4) {
                /* IPSR0_31_28 [4] */
                IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,
-               FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, 0,
+               FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR0_27_24 [4] */
                IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,
-               FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, 0,
+               FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR0_23_20 [4] */
@@ -3528,7 +3608,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, 0,
                /* IPSR0_19_16 [4] */
                IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,
-               0, 0, 0, 0,
+               0, FN_FSCLKST2x_A, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR0_15_12 [4] */
@@ -3542,7 +3622,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR0_7_4 [4] */
-               IFN_AVB_MAGIC, 0, FN_MSIOF2_S1_C, FN_SCK4_A,
+               IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
@@ -3561,38 +3641,38 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, FN_PWM3_A, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_27_24 [4] */
-               IFN_PWM2_A, FN_PWMFSW0, FN_A20, FN_HTX3_D,
+               IFN_PWM2_A, 0, 0, FN_HTX3_D,
                0, 0, 0, 0,
                0, FN_IETX_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_23_20 [4] */
-               IFN_PWM1_A, 0, FN_A21, FN_HRX3_D,
+               IFN_PWM1_A, 0, 0, FN_HRX3_D,
                FN_VI4_DATA7_B, 0, 0, 0,
                0, FN_IERX_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_19_16 [4] */
-               IFN_PWM0, FN_AVB_AVTP_PPS, FN_A22, 0,
+               IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0,
                FN_VI4_DATA6_B, 0, 0, 0,
                0, FN_IECLK_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_15_12 [4] */
-               IFN_IRQ5, FN_QSTB_QHE, FN_A23, FN_DU_EXVSYNC_DU_VSYNC,
-               FN_VI4_DATA5_B, 0, 0, 0,
+               IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC,
+               FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E,
                0, FN_PWM6_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_11_8 [4] */
-               IFN_IRQ4, FN_QSTH_QHS, FN_A24, FN_DU_EXHSYNC_DU_HSYNC,
-               FN_VI4_DATA4_B, 0, 0, 0,
+               IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC,
+               FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E,
                0, FN_PWM5_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_7_4 [4] */
-               IFN_IRQ3, FN_QSTVB_QVE, FN_A25, FN_DU_DOTCLKOUT1,
-               FN_VI4_DATA3_B, 0, 0,
+               IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1,
+               FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E,
                0, FN_PWM4_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR1_3_0 [4] */
                IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
-               FN_VI4_DATA2_B, 0, 0, 0,
+               FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E,
                0, FN_PWM3_B, 0, 0,
                0, 0, 0, 0
                }
@@ -3671,7 +3751,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IPSR3_11_8 [4] */
                IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,
                FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,
-               FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0,
+               FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0,
                0, 0, 0, 0,
                /* IPSR3_7_4 [4] */
                IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,
@@ -3864,27 +3944,27 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
                /* IPSR8_31_28 [4] */
-               IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, 0,
+               IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B,
                0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR8_27_24 [4] */
-               IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, 0,
+               IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B,
                0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR8_23_20 [4] */
-               IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, 0,
+               IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B,
                0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR8_19_16 [4] */
-               IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, 0,
+               IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B,
                0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR8_15_12 [4] */
-               IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, 0,
+               IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B,
                0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
@@ -3908,86 +3988,86 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
                /* IPSR9_31_28 [4] */
-               IFN_SD3_DAT5, FN_SD2_WP_A, 0, 0,
+               IFN_SD3_CLK, 0, FN_NFWEx, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_27_24 [4] */
-               IFN_SD3_DAT4, FN_SD2_CD_A, 0, 0,
-               0, 0, 0, 0,
+               IFN_SD2_DS, 0, FN_NFALE, 0,
                0, 0, 0, 0,
+               FN_SATA_DEVSLP_B, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_23_20 [4] */
-               IFN_SD2_DS, 0, 0, 0,
+               IFN_SD2_DAT3, 0, FN_NFDATA13, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               FN_SATA_DEVSLP_B, 0, 0, FN_VSP_A,
                0, 0, 0, 0,
                /* IPSR9_19_16 [4] */
-               IFN_SD2_DAT3, 0, 0, 0,
+               IFN_SD2_DAT2, 0, FN_NFDATA12, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               0, FN_SDATA_A, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_15_12 [4] */
-               IFN_SD2_DAT2, 0, 0, 0,
+               IFN_SD2_DAT1, 0, FN_NFDATA11, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               0, FN_MDATA_A, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_11_8 [4] */
-               IFN_SD2_DAT1, 0, 0, 0,
+               IFN_SD2_DAT0, 0, FN_NFDATA10, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               0, FN_STMx_A, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_7_4 [4] */
-               IFN_SD2_DAT0, 0, 0, 0,
+               IFN_SD2_CMD, 0, FN_NFDATA9, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               0, FN_MTSx_A, 0, 0,
                0, 0, 0, 0,
                /* IPSR9_3_0 [4] */
-               IFN_SD2_CLK, 0, 0, 0,
+               IFN_SD2_CLK, 0, FN_NFDATA8, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
-               0, FN_SCKZ_A, 0, 0,
                0, 0, 0, 0,
                }
        },
        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
                /* IPSR10_31_28 [4] */
-               IFN_RX0, FN_HRX1_B, 0, 0,
-               0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
+               IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_27_24 [4] */
-               IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
-               FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM__C, FN_RIF0_CLK_B,
-               0, FN_ADICHS2, 0, 0,
+               IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_23_20 [4] */
-               IFN_SD1_WP, 0, 0, 0,
-               0, FN_SIM0_D_B, 0, 0,
+               IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_19_16 [4] */
-               IFN_SD1_CD, 0, 0, 0,
-               0, FN_SIM0_CLK_B, 0, 0,
+               IFN_SD3_DAT3, 0, FN_NFDATA3, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_15_12 [4] */
-               IFN_SD0_WP, 0, 0, 0,
-               FN_SDA2_B, 0, 0, 0,
+               IFN_SD3_DAT2, 0, FN_NFDATA2, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_11_8 [4] */
-               IFN_SD0_CD, 0, 0, 0,
-               FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
+               IFN_SD3_DAT1, 0, FN_NFDATA1, 0,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_7_4 [4] */
-               IFN_SD3_DAT7, FN_SD3_WP, 0, 0,
+               IFN_SD3_DAT0, 0, FN_NFDATA0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                /* IPSR10_3_0 [4] */
-               IFN_SD3_DAT6, FN_SD3_CD, 0, 0,
+               IFN_SD3_CMD, 0, FN_NFREx, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
@@ -3996,268 +4076,311 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
                /* IPSR11_31_28 [4] */
+               IFN_RX0, FN_HRX1_B, 0, 0,
+               0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_27_24 [4] */
+               IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
+               FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B,
+               FN_ADICHS2, FN_SCK5_B, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_23_20 [4] */
+               IFN_SD1_WP, 0, FN_NFCEx_A, 0,
+               0, FN_SIM0_D_B, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_19_16 [4] */
+               IFN_SD1_CD, 0, FN_NFRBx_A, 0,
+               0, FN_SIM0_CLK_B, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_15_12 [4] */
+               IFN_SD0_WP, 0, FN_NFDATA15_A, 0,
+               FN_SDA2_B, 0, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_11_8 [4] */
+               IFN_SD0_CD, 0, FN_NFDATA14_A, 0,
+               FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_7_4 [4] */
+               IFN_SD3_DS, 0, FN_NFCLE, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               /* IPSR11_3_0 [4] */
+               IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               0, 0, 0, 0,
+               }
+       },
+       { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
+                               4, 4, 4, 4, 4, 4, 4, 4) {
+               /* IPSR12_31_28 [4] */
                IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,
                0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
                0, FN_ADICLK, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_27_24 [4] */
+               /* IPSR12_27_24 [4] */
                IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,
                0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,
                0, FN_ADICHS0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_23_20 [4] */
+               /* IPSR12_23_20 [4] */
                IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,
                0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,
                0, FN_ADIDATA, 0, 0,
-               /* IPSR11_19_16 [4] */
+               0, 0, 0, 0,
+               /* IPSR12_19_16 [4] */
                IFN_TX1_A, FN_HTX1_A, 0, 0,
                0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_15_12 [4] */
+               /* IPSR12_15_12 [4] */
                IFN_RX1_A, FN_HRX1_A, 0, 0,
-               0, FN_TS_SDAT0_C, FN_STP_IDS_0_C, FN_RIF1_CLK_C,
+               0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_11_8 [4] */
+               /* IPSR12_11_8 [4] */
                IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,
                FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,
                0, FN_ADICHS1, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_7_4 [4] */
+               /* IPSR12_7_4 [4] */
                IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,
                0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
                FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,
                0, 0, 0, 0,
-               /* IPSR11_3_0 [4] */
+               /* IPSR12_3_0 [4] */
                IFN_TX0, FN_HTX1_B, 0, 0,
                0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,
                0, 0, 0, 0,
-               0, 0, 0, 0,
                }
        },
-       { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
+       { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
-               /* IPSR12_31_28 [4] */
+               /* IPSR13_31_28 [4] */
                IFN_MSIOF0_SYNC, 0, 0, 0,
                0, 0, 0, 0,
-               FN_AUDIO_CLKOUT_A, 0, 0, 0,
-               0, 0, 0, 0,
-               /* IPSR12_27_24 [4] */
+               FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0,
+               0, FN_BPFCLK_D, 0, 0,
+               /* IPSR13_27_24 [4] */
                IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,
                FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,
                FN_AUDIO_CLKOUT2_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR12_23_20 [4] */
+               /* IPSR13_23_20 [4] */
                IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,
-               FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D,
-               FN_RIF0_SYNC_C,
-               FN_AUDIO_CLKOUT1_A, FN_AD_NSCx, 0, 0,
+               FN_SSI_SCK9_A, FN_TS_SPSYNC0_D,
+               FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C,
+               FN_AUDIO_CLKOUT1_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR12_19_16 [4] */
+               /* IPSR13_19_16 [4] */
                IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,
                FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,
-               0, FN_AD_DO, 0, 0,
                0, 0, 0, 0,
-               /* IPSR12_15_12 [4] */
+               0, 0, 0, 0,
+               /* IPSR13_15_12 [4] */
                IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,
-               FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
-               0, FN_AD_DI, 0, 0,
+               FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
                0, 0, 0, 0,
-               /* IPSR12_11_8 [4] */
+               0, 0, 0, 0,
+               /* IPSR13_11_8 [4] */
                IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,
                FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,
-               0, FN_AD_CLK, 0, 0,
+               0, 0, FN_RX5_B, 0,
                0, 0, 0, 0,
-               /* IPSR12_7_4 [4] */
+               /* IPSR13_7_4 [4] */
                IFN_RX2_A, 0, 0, FN_SD2_WP_B,
-               FN_SDA1_A, FN_RDS_DATA_B, FN_RMIN_A, FN_RIF1_SYNC_C,
-               0, FN_FSO_CEF_1_B, 0, 0,
+               FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C,
+               0, FN_FSO_CFE_1x, 0, 0,
                0, 0, 0, 0,
-               /* IPSR12_3_0 [4] */
+               /* IPSR13_3_0 [4] */
                IFN_TX2_A, 0, 0, FN_SD2_CD_B,
-               FN_SCL1_A, FN_RSD_CLK_B, FN_FMCLK_A, FN_RIF1_D1_C,
-               0, FN_FSO_CFE_0_B, 0, 0,
-               0, 0, 0, 0,
+               FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C,
+               0, FN_FSO_CFE_0x, 0, 0,
                }
        },
-       { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
+       { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
-               /* IPSR13_31_28 [4] */
+               /* IPSR14_31_28 [4] */
                IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,
                0, 0, 0, FN_MOUT2,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_27_24 [4] */
-               IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0,
-               0, 0, 0, FN_MOUT1,
+               /* IPSR14_27_24 [4] */
+               IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0,
+               0, 0, 0, 0, FN_MOUT1,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_23_20 [4] */
-               IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0,
+               /* IPSR14_23_20 [4] */
+               IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0,
                0, 0, 0, FN_MOUT0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_19_16 [4] */
+               /* IPSR14_19_16 [4] */
                IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_15_12 [4] */
+               /* IPSR14_15_12 [4] */
                IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,
                FN_SDA1_B, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_11_8 [4] */
+               /* IPSR14_11_8 [4] */
                IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,
                FN_SCL1_B, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR13_7_4 [4] */
-               IFN_MSIOF0_SS2, FN_TX5, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
-               FN_SSI_WS2_A, FN_RDS_DATA_A, FN_STP_OPWM_0_D, 0,
+               /* IPSR14_7_4 [4] */
+               IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
+               FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0,
                FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,
-               /* IPSR13_3_0 [4] */
-               IFN_MSIOF0_SS1, FN_RX5, 0, FN_AUDIO_CLKA_C,
-               FN_SSI_SCK2_A, FN_RDS_CLK_A, FN_STP_IVCXO27_0_C, 0,
+               0, 0, 0, 0,
+               /* IPSR14_3_0 [4] */
+               IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C,
+               FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0,
                FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,
                0, 0, 0, 0,
                }
        },
-       { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
+       { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
-               /* IPSR14_31_28 [4] */
+               /* IPSR15_31_28 [4] */
                IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,
                0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,
                FN_RIF2_D1_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_27_24 [4] */
+               /* IPSR15_27_24 [4] */
                IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,
                0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,
                FN_RIF2_SYNC_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_23_20 [4] */
+               /* IPSR15_23_20 [4] */
                IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,
                0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
                FN_RIF2_CLK_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_19_16 [4] */
+               /* IPSR15_19_16 [4] */
                IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,
                0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,
                FN_RIF2_D0_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_15_12 [4] */
+               /* IPSR15_15_12 [4] */
                IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,
                0, 0, FN_STP_IVCXO27_0_A, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_11_8 [4] */
+               /* IPSR15_11_8 [4] */
                IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,
                0, 0, FN_STP_OPWM_0_A, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_7_4 [4] */
+               /* IPSR15_7_4 [4] */
                IFN_SSI_SDATA2_A, 0, 0, 0,
                FN_SSI_SCK1_B, 0, 0, FN_MOUT6,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR14_3_0 [4] */
+               /* IPSR15_3_0 [4] */
                IFN_SSI_SDATA1_A, 0, 0, 0,
                0, 0, 0, FN_MOUT5,
                0, 0, 0, 0,
                0, 0, 0, 0,
                }
        },
-       { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
+       { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
-               /* IPSR15_31_28 [4] */
+               /* IPSR16_31_28 [4] */
                IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,
-               FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,
+               FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_27_24 [4] */
+               /* IPSR16_27_24 [4] */
                IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,
                0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,
-               FN_EIF3_D1_A, 0, 0, 0,
+               FN_RIF3_D1_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_23_20 [4] */
+               /* IPSR16_23_20 [4] */
                IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,
-               0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A,
+               0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A,
                FN_RIF3_D0_A, 0, FN_TCLK2_A, 0,
-               /* IPSR15_19_16 [4] */
+               0, 0, 0, 0,
+               /* IPSR16_19_16 [4] */
                IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,
-               0, FN_TS_SDT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
+               0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
                FN_RIF3_SYNC_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_15_12 [4] */
+               /* IPSR16_15_12 [4] */
                IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,
                0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,
                FN_RIF3_CLK_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_11_8 [4] */
+               /* IPSR16_11_8 [4] */
                IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,
-               0, 0, FN_RSD_DATA_C, 0,
+               0, 0, 0, 0,
                FN_SATA_DEVSLP_A, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_7_4 [4] */
-               IFN_SSI_WS6, FN_USB2_OVC, 0, FN_SIM0_D_D,
+               /* IPSR16_7_4 [4] */
+               IFN_SSI_WS6, 0, 0, FN_SIM0_D_D,
                0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
-               /* IPSR15_3_0 [4] */
-               IFN_SSI_SCK6, FN_USB2_PWEN, 0, FN_SIM0_RST_D,
-               0, 0, FN_RDS_CLK_C, 0,
+               /* IPSR16_3_0 [4] */
+               IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D,
+               0, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, 0,
                }
-
        },
-       { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
+       { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
                                4, 4, 4, 4, 4, 4, 4, 4) {
-               /* IPSR16_31_28 [4] */
-               IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0,
-               FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D,
-               FN_STP_IVCXO27_0_E,
-               FN_RIF3_D1_B, FN_SDATA_B, FN_RSO_TOE_B, FN_TPU0TO1,
+               /* IPSR17_31_28 [4] */
+               IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B,
+               FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E,
+               FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1,
                0, 0, 0, 0,
-               /* IPSR16_27_24 [4] */
+               /* IPSR17_27_24 [4] */
                IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,
                FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
-               FN_RIF3_D0_B, FN_MDATA_B, FN_TCLK2_B, FN_TPU0TO0,
-               0, 0, 0, 0,
-               /* IPSR16_23_20 [4] */
+               FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0,
+               FN_BPFCLK_C, FN_HRTS2x_C, 0, 0,
+               /* IPSR17_23_20 [4] */
                IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,
                FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
-               FN_RIF2_SYNC_B, FN_STMx_B, FN_REMOCON_B, 0,
-               0, 0, 0, 0,
-               /* IPSR16_19_16 [4] */
+               FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0,
+               0, FN_HCTS2x_C, 0, 0,
+               /* IPSR17_19_16 [4] */
                IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,
                FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
-               FN_RIF2_CLK_B, FN_MTSx_B, FN_SPEEDIN_A, FN_VSP_D,
-               0, 0, 0, 0,
-               /* IPSR16_15_12 [4] */
+               FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0,
+               0, FN_HTX2_C, 0, 0,
+               /* IPSR17_15_12 [4] */
                IFN_USB0_OVC, 0, 0, FN_SIM0_D_C,
                0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,
-               FN_RIF3_SYNC_B, 0, 0, FN_VSP_C,
-               0, 0, 0, 0,
-               /* IPSR16_11_8 [4] */
+               FN_RIF3_SYNC_B, 0, 0, 0,
+               0, FN_HRX2_C, 0, 0,
+               /* IPSR17_11_8 [4] */
                IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,
                0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
-               FN_RIF3_CLK_B, FN_SCKZ_B, 0, 0,
-               0, 0, 0, 0,
-               /* IPSR16_7_4 [4] */
+               FN_RIF3_CLK_B, 0, 0, 0,
+               0, FN_HSCK2_C, 0, 0,
+               /* IPSR17_7_4 [4] */
                IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,
-               FN_DVC_MUTE, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
-               0, 0, FN_TCLK1_A, FN_VSP_B,
+               0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
+               0, 0, FN_TCLK1_A, 0,
                0, 0, 0, 0,
-               /* IPSR16_3_0 [4] */
+               /* IPSR17_3_0 [4] */
                IFN_AUDIO_CLKA_A, 0, 0, 0,
                0, 0, 0, 0,
                0, 0, 0, FN_CC5_OSCOUT,
                0, 0, 0, 0,
                }
        },
-       { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
+       { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32,
                                1, 1, 1, 1, 1, 1, 1, 1,
                                1, 1, 1, 1, 1, 1, 1, 1,
                                1, 1, 1, 1, 1, 1, 1, 1,
@@ -4289,201 +4412,195 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                0, 0,
                0, 0,
-               /* IPSR17_7_4 [4] */
-               IFN_USB31_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,
+               /* IPSR18_7_4 [4] */
+               IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,
                FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,
                FN_RIF2_D1_B, 0, 0, FN_TPU0TO3,
-               0, 0, 0, 0,
-               /* IPSR17_3_0 [4] */
-               IFN_USB31_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,
-               FN_SI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
+               FN_FMIN_C, FN_FMIN_D, 0, 0,
+               /* IPSR18_3_0 [4] */
+               IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,
+               FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
                FN_RIF2_D0_B, 0, 0, FN_TPU0TO2,
-               0, 0, 0, 0,
+               FN_FMCLK_C, FN_FMCLK_D, 0, 0,
                }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32,
-                               1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2,
-                               1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
-               /* RESERVED [1] */
-               0, 0,
-               /* SEL_MSIOF3 [2] */
+                               3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
+                               1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) {
+               /* MOD_SEL0 */
+               /* sel_msiof3[3](0,1,2,3,4) */
                FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
                FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
-               /* SEL_MSIOF2 [2] */
+               FN_SEL_MSIOF3_4, 0,
+               0, 0,
+               /* sel_msiof2[2](0,1,2,3) */
                FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
                FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
-               /* SEL_MSIOF1 [3] */
+               /* sel_msiof1[3](0,1,2,3,4,5,6) */
                FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
                FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
                FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
                FN_SEL_MSIOF1_6, 0,
-               /* SEL_LBSC [1] */
+               /* sel_lbsc[1](0,1) */
                FN_SEL_LBSC_0, FN_SEL_LBSC_1,
-               /* SEL_IEBUS [1] */
+               /* sel_iebus[1](0,1) */
                FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
-               /* SEL_I2C6 [2] */
-               FN_SEL_I2C6_0, FN_SEL_I2C6_1,
-               FN_SEL_I2C6_2, 0,
-               /* SEL_I2C2 [1] */
+               /* sel_i2c2[1](0,1) */
                FN_SEL_I2C2_0, FN_SEL_I2C2_1,
-               /* SEL_I2C1 [1] */
+               /* sel_i2c1[1](0,1) */
                FN_SEL_I2C1_0, FN_SEL_I2C1_1,
-               /* SEL_HSCIF4 [1] */
+               /* sel_hscif4[1](0,1) */
                FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
-               /* SEL_HSCIF3 [2] */
+               /* sel_hscif3[2](0,1,2,3) */
                FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
                FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
-               /* SEL_HSCIF2 [1] */
-               FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
-               /* SEL_HSCIF1 [1] */
+               /* sel_hscif1[1](0,1) */
                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
-               /* SEL_FSO [1] */
-               0, FN_SEL_FSO_1,
-               /* SEL_FM [1] */
-               FN_SEL_FM_0, FN_SEL_FM_1,
-               /* SEL_ETHERAVB [1] */
+               /* reserved[1] */
+               0, 0,
+               /* sel_hscif2[2](0,1,2) */
+               FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+               FN_SEL_HSCIF2_2, 0,
+               /* sel_etheravb[1](0,1) */
                FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
-               /* SEL_DRIF3 [1] */
+               /* sel_drif3[1](0,1) */
                FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
-               /* SEL_DRIF2 [1] */
+               /* sel_drif2[1](0,1) */
                FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
-               /* SEL_DRIF1 [2] */
+               /* sel_drif1[2](0,1,2) */
                FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
                FN_SEL_DRIF1_2, 0,
-               /* SEL_DRIF0 [2] */
+               /* sel_drif0[2](0,1,2) */
                FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
                FN_SEL_DRIF0_2, 0,
-               /* SEL_CANFD0 [1] */
+               /* sel_canfd0[1](0,1) */
                FN_SEL_CANFD_0, FN_SEL_CANFD_1,
-               /* SEL_ADG [2] */
-               FN_SEL_ADG_0, FN_SEL_ADG_1,
-               FN_SEL_ADG_2, FN_SEL_ADG_3,
-               /* SEL_5LINE [1] */
-               FN_SEL_5LINE_0, FN_SEL_5LINE_1,
+               /* sel_adg_a[2](0,1,2) */
+               FN_SEL_ADG_A_0, FN_SEL_ADG_A_1,
+               FN_SEL_ADG_A_2, 0,
+               /* reserved[3]*/
+               0, 0,
+               0, 0,
+               0, 0,
                }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32,
                                2, 3, 1, 2,
                                3, 1, 1, 2, 1,
-                               2, 1, 1, 1, 1, 1, 2,
-                               1, 1, 1, 1, 1, 1, 1) {
-               /* SEL_TSIF1 [2] */
-               FN_SEL_TSIF1_0,
-               FN_SEL_TSIF1_1,
-               FN_SEL_TSIF1_2,
-               FN_SEL_TSIF1_3,
-               /* SEL_TSIF0 [3] */
-               FN_SEL_TSIF0_0,
-               FN_SEL_TSIF0_1,
-               FN_SEL_TSIF0_2,
-               FN_SEL_TSIF0_3,
-               FN_SEL_TSIF0_4,
-               0,
-               0,
-               0,
-               /* SEL_TIMER_TMU [1] */
-               FN_SEL_TIMER_TMU_0,
-               FN_SEL_TIMER_TMU_1,
-               /* SEL_SSP1_1 [2] */
-               FN_SEL_SSP1_1_0,
-               FN_SEL_SSP1_1_1,
-               FN_SEL_SSP1_1_2,
-               FN_SEL_SSP1_1_3,
-               /* SEL_SSP1_0 [3] */
-               FN_SEL_SSP1_0_0,
-               FN_SEL_SSP1_0_1,
-               FN_SEL_SSP1_0_2,
-               FN_SEL_SSP1_0_3,
-               FN_SEL_SSP1_0_4,
-               0,
-               0,
-               0,
-               /* SEL_SSI [1] */
-               FN_SEL_SSI_0,
-               FN_SEL_SSI_1,
-               /* SEL_SPEED_PULSE_IF [1] */
-               FN_SEL_SPEED_PULSE_IF_0,
-               FN_SEL_SPEED_PULSE_IF_1,
-               /* SEL_SIMCARD [2] */
-               FN_SEL_SIMCARD_0,
-               FN_SEL_SIMCARD_1,
-               FN_SEL_SIMCARD_2,
-               FN_SEL_SIMCARD_3,
-               /* SEL_SDHI2 [1] */
-               FN_SEL_SDHI2_0,
-               FN_SEL_SDHI2_1,
-               /* SEL_SCIF4 [2] */
-               FN_SEL_SCIF4_0,
-               FN_SEL_SCIF4_1,
-               FN_SEL_SCIF4_2,
-               0,
-               /* SEL_SCIF3 [1] */
-               FN_SEL_SCIF3_0,
-               FN_SEL_SCIF3_1,
-               /* SEL_SCIF2 [1] */
-               FN_SEL_SCIF2_0,
-               FN_SEL_SCIF2_1,
-               /* SEL_SCIF1 [1] */
-               FN_SEL_SCIF1_0,
-               FN_SEL_SCIF1_1,
-               /* SEL_SCIF [1] */
-               FN_SEL_SCIF_0,
-               FN_SEL_SCIF_1,
-               /* SEL_REMOCON [1] */
-               FN_SEL_REMOCON_0,
-               FN_SEL_REMOCON_1,
-               /* SEL_RDS [2] */
-               FN_SEL_RDS_0,
-               FN_SEL_RDS_1,
-               FN_SEL_RDS_2,
-               0,
-               /* SEL_RCAN [1] */
-               FN_SEL_RCAN_0,
-               FN_SEL_RCAN_1,
-               /* SEL_PWM6 [1] */
-               FN_SEL_PWM6_0,
-               FN_SEL_PWM6_1,
-               /* SEL_PWM5 [1] */
-               FN_SEL_PWM5_0,
-               FN_SEL_PWM5_1,
-               /* SEL_PWM4 [1] */
-               FN_SEL_PWM4_0,
-               FN_SEL_PWM4_1,
-               /* SEL_PWM3 [1] */
-               FN_SEL_PWM3_0,
-               FN_SEL_PWM3_1,
-               /* SEL_PWM2 [1] */
-               FN_SEL_PWM2_0,
-               FN_SEL_PWM2_1,
-               /* SEL_PWM1 [1] */
-               FN_SEL_PWM1_0,
-               FN_SEL_PWM1_1,
+                               2, 1, 1, 1, 1, 1, 1,
+                               1, 1, 1, 1, 1, 1, 1, 1) {
+               /* sel_tsif1[2](0,1,2,3) */
+               FN_SEL_TSIF1_0, FN_SEL_TSIF1_1,
+               FN_SEL_TSIF1_2, FN_SEL_TSIF1_3,
+               /* sel_tsif0[3](0,1,2,3,4) */
+               FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
+               FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+               FN_SEL_TSIF0_4, 0,
+               0, 0,
+               /* sel_timer_tmu1[1](0,1) */
+               FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1,
+               /* sel_ssp1_1[2](0,1,2,3) */
+               FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1,
+               FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3,
+               /* sel_ssp1_0[3](0,1,2,3,4) */
+               FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1,
+               FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3,
+               FN_SEL_SSP1_0_4, 0,
+               0, 0,
+               /* sel_ssi1[1](0,1) */
+               FN_SEL_SSI_0, FN_SEL_SSI_1,
+               /* sel_speed_pulse_if[1](0,1) */
+               FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1,
+               /* sel_simcard[2](0,1,2,3) */
+               FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1,
+               FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3,
+               /* sel_sdhi2[1](0,1) */
+               FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
+               /* sel_scif4[2](0,1,2) */
+               FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
+               FN_SEL_SCIF4_2, 0,
+               /* sel_scif3[1](0,1) */
+               FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
+               /* sel_scif2[1](0,1) */
+               FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
+               /* sel_scif1[1](0,1) */
+               FN_SEL_SCIF1_0, FN_SEL_SCIF1_1,
+               /* sel_scif[1](0,1) */
+               FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+               /* sel_remocon[1](0,1) */
+               FN_SEL_REMOCON_0, FN_SEL_REMOCON_1,
+               /* reserved[8..7] */
+               0, 0,
+               0, 0,
+               /* sel_rcan0[1](0,1) */
+               FN_SEL_RCAN_0, FN_SEL_RCAN_1,
+               /* sel_pwm6[1](0,1) */
+               FN_SEL_PWM6_0, FN_SEL_PWM6_1,
+               /* sel_pwm5[1](0,1) */
+               FN_SEL_PWM5_0, FN_SEL_PWM5_1,
+               /* sel_pwm4[1](0,1) */
+               FN_SEL_PWM4_0, FN_SEL_PWM4_1,
+               /* sel_pwm3[1](0,1) */
+               FN_SEL_PWM3_0, FN_SEL_PWM3_1,
+               /* sel_pwm2[1](0,1) */
+               FN_SEL_PWM2_0, FN_SEL_PWM2_1,
+               /* sel_pwm1[1](0,1) */
+               FN_SEL_PWM1_0, FN_SEL_PWM1_1,
                }
        },
        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32,
-                               1, 1, 1, 26, 2, 1) {
-               /* I2C_SEL_5 [1] */
-               FN_I2C_SEL_5_0,
-               FN_I2C_SEL_5_1,
-               /* I2C_SEL_3 [1] */
-               FN_I2C_SEL_3_0,
-               FN_I2C_SEL_3_1,
-               /* I2C_SEL_0 [1] */
-               FN_I2C_SEL_0_0,
-               FN_I2C_SEL_0_1,
-               /* reserved [26] */
-               /* SEL_VSP [2] */
-               FN_SEL_VSP_0,
-               FN_SEL_VSP_1,
-               FN_SEL_VSP_2,
-               FN_SEL_VSP_3,
-               /* SEL_VIN4 [1] */
-               FN_SEL_VIN4_0,
-               FN_SEL_VIN4_1,
+                       1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
+                       1, 1, 1, 1, 1, 1, 1, 1,
+                       1, 1, 1, 1, 1, 1, 1, 1) {
+               /* i2c_sel_5[1](0,1) */
+               FN_I2C_SEL_5_0, FN_I2C_SEL_5_1,
+               /* i2c_sel_3[1](0,1) */
+               FN_I2C_SEL_3_0, FN_I2C_SEL_3_1,
+               /* i2c_sel_0[1](0,1) */
+               FN_I2C_SEL_0_0, FN_I2C_SEL_0_1,
+               /* sel_fm[2](0,1,2,3) */
+               FN_SEL_FM_0, FN_SEL_FM_1,
+               FN_SEL_FM_2, FN_SEL_FM_3,
+               /* sel_scif5[1](0,1) */
+               FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+               /* sel_i2c6[3](0,1,2) */
+               FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+               FN_SEL_I2C6_2, 0,
+               /* sel_ndfc[1](0,1) */
+               FN_SEL_NDFC_0, FN_SEL_NDFC_1,
+               /* sel_ssi2[1](0,1) */
+               FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+               /* sel_ssi9[1](0,1) */
+               FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+               /* sel_timer_tmu2[1](0,1) */
+               FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1,
+               /* sel_adg_b[1](0,1) */
+               FN_SEL_ADG_B_0, FN_SEL_ADG_B_1,
+               /* sel_adg_c[1](0,1) */
+               FN_SEL_ADG_C_0, FN_SEL_ADG_C_1,
+               /* reserved[16..16] */
+               0, 0,
+               /* reserved[15..8] */
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               /* reserved[7..1] */
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               0, 0,
+               /* sel_vin4[1](0,1) */
+               FN_SEL_VIN4_0, FN_SEL_VIN4_1,
                }
        },
-
-       /* under construction */
        { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
                0, 0,
                0, 0,
@@ -4525,7 +4642,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                0, 0,
                0, 0,
-               0, 0,
+               GP_1_28_IN, GP_1_28_OUT,
                GP_1_27_IN, GP_1_27_OUT,
                GP_1_26_IN, GP_1_26_OUT,
                GP_1_25_IN, GP_1_25_OUT,
@@ -4760,7 +4877,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
        },
        { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
-               0, 0, 0, 0,
+               0, 0, 0, GP_1_28_DATA,
                GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
                GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
                GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
@@ -4813,8 +4930,10 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                0, 0, 0, 0,
                GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
        },
+       { },
 };
 
+
 static struct pinmux_info r8a7795_pinmux_info = {
        .name = "r8a7795_pfc",
 
@@ -4828,7 +4947,7 @@ static struct pinmux_info r8a7795_pinmux_info = {
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
        .first_gpio = GPIO_GP_0_0,
-       .last_gpio = GPIO_FN_TPU0TO3,
+       .last_gpio = GPIO_FN_FMIN_D,
 
        .gpios = pinmux_gpios,
        .cfg_regs = pinmux_config_regs,
Domain: System / Kernel;