drm/amdkfd: add RAS capabilities in topology for Vega20 (v2)
authorEric Huang <JinhuiEric.Huang@amd.com>
Fri, 11 Jan 2019 19:52:22 +0000 (14:52 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 19 Mar 2019 20:36:51 +0000 (15:36 -0500)
It is to collaborate with HSA_CAPABILITY in libhsakmt.

v2: squash in NULL pointer check

Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
drivers/gpu/drm/amd/amdkfd/kfd_topology.h

index 09da916..2cb09e0 100644 (file)
@@ -37,6 +37,7 @@
 #include "kfd_device_queue_manager.h"
 #include "kfd_iommu.h"
 #include "amdgpu_amdkfd.h"
+#include "amdgpu_ras.h"
 
 /* topology_device_list - Master list of all topology devices */
 static struct list_head topology_device_list;
@@ -1197,6 +1198,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
        void *crat_image = NULL;
        size_t image_size = 0;
        int proximity_domain;
+       struct amdgpu_ras *ctx;
 
        INIT_LIST_HEAD(&temp_topology_device_list);
 
@@ -1328,6 +1330,20 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
                dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
        }
 
+       ctx = amdgpu_ras_get_context((struct amdgpu_device *)(dev->gpu->kgd));
+       if (ctx) {
+               /* kfd only concerns sram ecc on GFX/SDMA and HBM ecc on UMC */
+               dev->node_props.capability |=
+                       (((ctx->features & BIT(AMDGPU_RAS_BLOCK__SDMA)) != 0) ||
+                        ((ctx->features & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0)) ?
+                       HSA_CAP_SRAM_EDCSUPPORTED : 0;
+               dev->node_props.capability |= ((ctx->features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
+                       HSA_CAP_MEM_EDCSUPPORTED : 0;
+
+               dev->node_props.capability |= (ctx->features != 0) ?
+                       HSA_CAP_RASEVENTNOTIFY : 0;
+       }
+
        kfd_debug_print_topology();
 
        if (!res)
index 92a19be..84710cf 100644 (file)
 #define HSA_CAP_DOORBELL_TYPE_2_0              0x2
 #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP           0x00004000
 
+#define HSA_CAP_SRAM_EDCSUPPORTED              0x00080000
+#define HSA_CAP_MEM_EDCSUPPORTED               0x00100000
+#define HSA_CAP_RASEVENTNOTIFY                 0x00200000
+
 struct kfd_node_properties {
        uint64_t hive_id;
        uint32_t cpu_cores_count;