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Make sure that all state packets are handled in
authorMichel Daenzer <michel@daenzer.net>
Sat, 10 Jan 2004 20:59:16 +0000 (20:59 +0000)
committerMichel Daenzer <michel@daenzer.net>
Sat, 10 Jan 2004 20:59:16 +0000 (20:59 +0000)
    radeon_check_and_fixup_packets()
Fix state packet IDs of R200 cubic offsets

shared-core/radeon_state.c patch | blob | history
shared/radeon_state.c patch | blob | history

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 6e02654..0ed1f53 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -80,35 +80,56 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
                                                      drm_file_t *filp_priv,
                                                      int id,
                                                      u32 *data ) {
-       if ( id == RADEON_EMIT_PP_MISC &&
-            radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                &data[( RADEON_RB3D_DEPTHOFFSET
-                                                        - RADEON_PP_MISC ) / 4] ) ) {
-               DRM_ERROR( "Invalid depth buffer offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id == RADEON_EMIT_PP_CNTL &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[( RADEON_RB3D_COLOROFFSET
-                                                               - RADEON_PP_CNTL ) / 4] ) ) {
-               DRM_ERROR( "Invalid colour buffer offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id >= R200_EMIT_PP_TXOFFSET_0 &&
-                   id <= R200_EMIT_PP_TXOFFSET_5 &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[0] ) ) {
-               DRM_ERROR( "Invalid R200 texture offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( ( id == RADEON_EMIT_PP_TXFILTER_0 || id == RADEON_EMIT_PP_TXFILTER_1 ||
-                     id == RADEON_EMIT_PP_TXFILTER_2 /*|| id == RADEON_EMIT_PP_TXFILTER_3 ||
-                     id == RADEON_EMIT_PP_TXFILTER_4 || id == RADEON_EMIT_PP_TXFILTER_5*/ ) &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[( RADEON_PP_TXOFFSET_0
-                                                               - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
-               DRM_ERROR( "Invalid R100 texture offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id == R200_PP_CUBIC_OFFSET_F1_0 || id == R200_PP_CUBIC_OFFSET_F1_1 ||
-                   id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
-                   id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
+       switch ( id ) {
+
+       case RADEON_EMIT_PP_MISC:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_RB3D_DEPTHOFFSET
+                                                                - RADEON_PP_MISC ) / 4] ) ) {
+                       DRM_ERROR( "Invalid depth buffer offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case RADEON_EMIT_PP_CNTL:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_RB3D_COLOROFFSET
+                                                                - RADEON_PP_CNTL ) / 4] ) ) {
+                       DRM_ERROR( "Invalid colour buffer offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case R200_EMIT_PP_TXOFFSET_0:
+       case R200_EMIT_PP_TXOFFSET_1:
+       case R200_EMIT_PP_TXOFFSET_2:
+       case R200_EMIT_PP_TXOFFSET_3:
+       case R200_EMIT_PP_TXOFFSET_4:
+       case R200_EMIT_PP_TXOFFSET_5:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[0] ) ) {
+                       DRM_ERROR( "Invalid R200 texture offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case RADEON_EMIT_PP_TXFILTER_0:
+       case RADEON_EMIT_PP_TXFILTER_1:
+       case RADEON_EMIT_PP_TXFILTER_2:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_PP_TXOFFSET_0
+                                                                - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
+                       DRM_ERROR( "Invalid R100 texture offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case R200_EMIT_PP_CUBIC_OFFSETS_0:
+       case R200_EMIT_PP_CUBIC_OFFSETS_1:
+       case R200_EMIT_PP_CUBIC_OFFSETS_2:
+       case R200_EMIT_PP_CUBIC_OFFSETS_3:
+       case R200_EMIT_PP_CUBIC_OFFSETS_4:
+       case R200_EMIT_PP_CUBIC_OFFSETS_5: {
                int i;
                for ( i = 0; i < 5; i++ ) {
                        if ( radeon_check_and_fixup_offset_user( dev_priv,
@@ -118,6 +139,74 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
                                return DRM_ERR( EINVAL );
                        }
                }
+               break;
+       }
+
+       case RADEON_EMIT_RB3D_COLORPITCH:
+       case RADEON_EMIT_RE_LINE_PATTERN:
+       case RADEON_EMIT_SE_LINE_WIDTH:
+       case RADEON_EMIT_PP_LUM_MATRIX:
+       case RADEON_EMIT_PP_ROT_MATRIX_0:
+       case RADEON_EMIT_RB3D_STENCILREFMASK:
+       case RADEON_EMIT_SE_VPORT_XSCALE:
+       case RADEON_EMIT_SE_CNTL:
+       case RADEON_EMIT_SE_CNTL_STATUS:
+       case RADEON_EMIT_RE_MISC:
+       case RADEON_EMIT_PP_BORDER_COLOR_0:
+       case RADEON_EMIT_PP_BORDER_COLOR_1:
+       case RADEON_EMIT_PP_BORDER_COLOR_2:
+       case RADEON_EMIT_SE_ZBIAS_FACTOR:
+       case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
+       case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
+       case R200_EMIT_PP_TXCBLEND_0:
+       case R200_EMIT_PP_TXCBLEND_1:
+       case R200_EMIT_PP_TXCBLEND_2:
+       case R200_EMIT_PP_TXCBLEND_3:
+       case R200_EMIT_PP_TXCBLEND_4:
+       case R200_EMIT_PP_TXCBLEND_5:
+       case R200_EMIT_PP_TXCBLEND_6:
+       case R200_EMIT_PP_TXCBLEND_7:
+       case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
+       case R200_EMIT_TFACTOR_0:
+       case R200_EMIT_VTX_FMT_0:
+       case R200_EMIT_VAP_CTL:
+       case R200_EMIT_MATRIX_SELECT_0:
+       case R200_EMIT_TEX_PROC_CTL_2:
+       case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
+       case R200_EMIT_PP_TXFILTER_0:
+       case R200_EMIT_PP_TXFILTER_1:
+       case R200_EMIT_PP_TXFILTER_2:
+       case R200_EMIT_PP_TXFILTER_3:
+       case R200_EMIT_PP_TXFILTER_4:
+       case R200_EMIT_PP_TXFILTER_5:
+       case R200_EMIT_VTE_CNTL:
+       case R200_EMIT_OUTPUT_VTX_COMP_SEL:
+       case R200_EMIT_PP_TAM_DEBUG3:
+       case R200_EMIT_PP_CNTL_X:
+       case R200_EMIT_RB3D_DEPTHXY_OFFSET:
+       case R200_EMIT_RE_AUX_SCISSOR_CNTL:
+       case R200_EMIT_RE_SCISSOR_TL_0:
+       case R200_EMIT_RE_SCISSOR_TL_1:
+       case R200_EMIT_RE_SCISSOR_TL_2:
+       case R200_EMIT_SE_VAP_CNTL_STATUS:
+       case R200_EMIT_SE_VTX_STATE_CNTL:
+       case R200_EMIT_RE_POINTSIZE:
+       case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
+       case R200_EMIT_PP_CUBIC_FACES_0:
+       case R200_EMIT_PP_CUBIC_FACES_1:
+       case R200_EMIT_PP_CUBIC_FACES_2:
+       case R200_EMIT_PP_CUBIC_FACES_3:
+       case R200_EMIT_PP_CUBIC_FACES_4:
+       case R200_EMIT_PP_CUBIC_FACES_5:
+       case RADEON_EMIT_PP_TEX_SIZE_0:
+       case RADEON_EMIT_PP_TEX_SIZE_1:
+       case RADEON_EMIT_PP_TEX_SIZE_2:
+               /* These packets don't contain memory offsets */
+               break;
+
+       default:
+               DRM_ERROR( "Unknown state packet ID %d\n", id );
+               return DRM_ERR( EINVAL );
        }
 
        return 0;
diff --git a/shared/radeon_state.c b/shared/radeon_state.c
index 6e02654..0ed1f53 100644 (file)
--- a/shared/radeon_state.c
+++ b/shared/radeon_state.c
@@ -80,35 +80,56 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
                                                      drm_file_t *filp_priv,
                                                      int id,
                                                      u32 *data ) {
-       if ( id == RADEON_EMIT_PP_MISC &&
-            radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                &data[( RADEON_RB3D_DEPTHOFFSET
-                                                        - RADEON_PP_MISC ) / 4] ) ) {
-               DRM_ERROR( "Invalid depth buffer offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id == RADEON_EMIT_PP_CNTL &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[( RADEON_RB3D_COLOROFFSET
-                                                               - RADEON_PP_CNTL ) / 4] ) ) {
-               DRM_ERROR( "Invalid colour buffer offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id >= R200_EMIT_PP_TXOFFSET_0 &&
-                   id <= R200_EMIT_PP_TXOFFSET_5 &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[0] ) ) {
-               DRM_ERROR( "Invalid R200 texture offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( ( id == RADEON_EMIT_PP_TXFILTER_0 || id == RADEON_EMIT_PP_TXFILTER_1 ||
-                     id == RADEON_EMIT_PP_TXFILTER_2 /*|| id == RADEON_EMIT_PP_TXFILTER_3 ||
-                     id == RADEON_EMIT_PP_TXFILTER_4 || id == RADEON_EMIT_PP_TXFILTER_5*/ ) &&
-                   radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
-                                                       &data[( RADEON_PP_TXOFFSET_0
-                                                               - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
-               DRM_ERROR( "Invalid R100 texture offset\n" );
-               return DRM_ERR( EINVAL );
-       } else if ( id == R200_PP_CUBIC_OFFSET_F1_0 || id == R200_PP_CUBIC_OFFSET_F1_1 ||
-                   id == R200_PP_CUBIC_OFFSET_F1_2 || id == R200_PP_CUBIC_OFFSET_F1_3 ||
-                   id == R200_PP_CUBIC_OFFSET_F1_4 || id == R200_PP_CUBIC_OFFSET_F1_5 ) {
+       switch ( id ) {
+
+       case RADEON_EMIT_PP_MISC:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_RB3D_DEPTHOFFSET
+                                                                - RADEON_PP_MISC ) / 4] ) ) {
+                       DRM_ERROR( "Invalid depth buffer offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case RADEON_EMIT_PP_CNTL:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_RB3D_COLOROFFSET
+                                                                - RADEON_PP_CNTL ) / 4] ) ) {
+                       DRM_ERROR( "Invalid colour buffer offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case R200_EMIT_PP_TXOFFSET_0:
+       case R200_EMIT_PP_TXOFFSET_1:
+       case R200_EMIT_PP_TXOFFSET_2:
+       case R200_EMIT_PP_TXOFFSET_3:
+       case R200_EMIT_PP_TXOFFSET_4:
+       case R200_EMIT_PP_TXOFFSET_5:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[0] ) ) {
+                       DRM_ERROR( "Invalid R200 texture offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case RADEON_EMIT_PP_TXFILTER_0:
+       case RADEON_EMIT_PP_TXFILTER_1:
+       case RADEON_EMIT_PP_TXFILTER_2:
+               if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
+                                                        &data[( RADEON_PP_TXOFFSET_0
+                                                                - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
+                       DRM_ERROR( "Invalid R100 texture offset\n" );
+                       return DRM_ERR( EINVAL );
+               }
+               break;
+
+       case R200_EMIT_PP_CUBIC_OFFSETS_0:
+       case R200_EMIT_PP_CUBIC_OFFSETS_1:
+       case R200_EMIT_PP_CUBIC_OFFSETS_2:
+       case R200_EMIT_PP_CUBIC_OFFSETS_3:
+       case R200_EMIT_PP_CUBIC_OFFSETS_4:
+       case R200_EMIT_PP_CUBIC_OFFSETS_5: {
                int i;
                for ( i = 0; i < 5; i++ ) {
                        if ( radeon_check_and_fixup_offset_user( dev_priv,
@@ -118,6 +139,74 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
                                return DRM_ERR( EINVAL );
                        }
                }
+               break;
+       }
+
+       case RADEON_EMIT_RB3D_COLORPITCH:
+       case RADEON_EMIT_RE_LINE_PATTERN:
+       case RADEON_EMIT_SE_LINE_WIDTH:
+       case RADEON_EMIT_PP_LUM_MATRIX:
+       case RADEON_EMIT_PP_ROT_MATRIX_0:
+       case RADEON_EMIT_RB3D_STENCILREFMASK:
+       case RADEON_EMIT_SE_VPORT_XSCALE:
+       case RADEON_EMIT_SE_CNTL:
+       case RADEON_EMIT_SE_CNTL_STATUS:
+       case RADEON_EMIT_RE_MISC:
+       case RADEON_EMIT_PP_BORDER_COLOR_0:
+       case RADEON_EMIT_PP_BORDER_COLOR_1:
+       case RADEON_EMIT_PP_BORDER_COLOR_2:
+       case RADEON_EMIT_SE_ZBIAS_FACTOR:
+       case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
+       case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
+       case R200_EMIT_PP_TXCBLEND_0:
+       case R200_EMIT_PP_TXCBLEND_1:
+       case R200_EMIT_PP_TXCBLEND_2:
+       case R200_EMIT_PP_TXCBLEND_3:
+       case R200_EMIT_PP_TXCBLEND_4:
+       case R200_EMIT_PP_TXCBLEND_5:
+       case R200_EMIT_PP_TXCBLEND_6:
+       case R200_EMIT_PP_TXCBLEND_7:
+       case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
+       case R200_EMIT_TFACTOR_0:
+       case R200_EMIT_VTX_FMT_0:
+       case R200_EMIT_VAP_CTL:
+       case R200_EMIT_MATRIX_SELECT_0:
+       case R200_EMIT_TEX_PROC_CTL_2:
+       case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
+       case R200_EMIT_PP_TXFILTER_0:
+       case R200_EMIT_PP_TXFILTER_1:
+       case R200_EMIT_PP_TXFILTER_2:
+       case R200_EMIT_PP_TXFILTER_3:
+       case R200_EMIT_PP_TXFILTER_4:
+       case R200_EMIT_PP_TXFILTER_5:
+       case R200_EMIT_VTE_CNTL:
+       case R200_EMIT_OUTPUT_VTX_COMP_SEL:
+       case R200_EMIT_PP_TAM_DEBUG3:
+       case R200_EMIT_PP_CNTL_X:
+       case R200_EMIT_RB3D_DEPTHXY_OFFSET:
+       case R200_EMIT_RE_AUX_SCISSOR_CNTL:
+       case R200_EMIT_RE_SCISSOR_TL_0:
+       case R200_EMIT_RE_SCISSOR_TL_1:
+       case R200_EMIT_RE_SCISSOR_TL_2:
+       case R200_EMIT_SE_VAP_CNTL_STATUS:
+       case R200_EMIT_SE_VTX_STATE_CNTL:
+       case R200_EMIT_RE_POINTSIZE:
+       case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
+       case R200_EMIT_PP_CUBIC_FACES_0:
+       case R200_EMIT_PP_CUBIC_FACES_1:
+       case R200_EMIT_PP_CUBIC_FACES_2:
+       case R200_EMIT_PP_CUBIC_FACES_3:
+       case R200_EMIT_PP_CUBIC_FACES_4:
+       case R200_EMIT_PP_CUBIC_FACES_5:
+       case RADEON_EMIT_PP_TEX_SIZE_0:
+       case RADEON_EMIT_PP_TEX_SIZE_1:
+       case RADEON_EMIT_PP_TEX_SIZE_2:
+               /* These packets don't contain memory offsets */
+               break;
+
+       default:
+               DRM_ERROR( "Unknown state packet ID %d\n", id );
+               return DRM_ERR( EINVAL );
        }
 
        return 0;
Domain: Graphics System / Uncategorized;