Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
-/// FIXME: Remove once the transition to Align is over.
-inline unsigned inferAlignmentFromPtrInfo(MachineFunction &MF,
- const MachinePointerInfo &MPO) {
- return inferAlignFromPtrInfo(MF, MPO).value();
-}
-
/// Return the least common multiple type of \p Ty0 and \p Ty1, by changing
/// the number of vector elements or scalar bitwidth. The intent is a
/// G_MERGE_VALUES can be constructed from \p Ty0 elements, and unmerged into
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
- unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
- Align);
+ inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}
.getReg(0);
}
MachineFunction &MF = MIRBuilder.getMF();
- unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
- auto MMO = MF.getMachineMemOperand(
- MPO, MachineMemOperand::MOStore, Size, Align);
+ auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size,
+ inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildStore(ValVReg, Addr, *MMO);
}
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
- unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
// FIXME: Get alignment
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
- Align);
+ inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}
return B.buildPtrAdd(PtrType, KernArgSegmentVReg, OffsetReg).getReg(0);
}
-void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
- Type *ParamTy, uint64_t Offset,
- unsigned Align,
+void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, Type *ParamTy,
+ uint64_t Offset, Align Alignment,
Register DstReg) const {
MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
Register PtrReg = lowerParameterPtr(B, ParamTy, Offset);
- MachineMemOperand *MMO =
- MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
- MachineMemOperand::MODereferenceable |
- MachineMemOperand::MOInvariant,
- TypeSize, Align);
+ MachineMemOperand *MMO = MF.getMachineMemOperand(
+ PtrInfo,
+ MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
+ MachineMemOperand::MOInvariant,
+ TypeSize, Alignment);
B.buildLoad(DstReg, PtrReg, *MMO);
}
allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
unsigned i = 0;
- const unsigned KernArgBaseAlign = 16;
+ const Align KernArgBaseAlign(16);
const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
uint64_t ExplicitArgOffset = 0;
OrigArgRegs.size() == 1
? OrigArgRegs[0]
: MRI.createGenericVirtualRegister(getLLTForType(*ArgTy, DL));
- unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
+ Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
- lowerParameter(B, ArgTy, ArgOffset, Align, ArgReg);
+ lowerParameter(B, ArgTy, ArgOffset, Alignment, ArgReg);
if (OrigArgRegs.size() > 1)
unpackRegs(OrigArgRegs, ArgReg, ArgTy, B);
++i;
uint64_t Offset) const;
void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
- unsigned Align, Register DstReg) const;
+ Align Alignment, Register DstReg) const;
/// A function of this type is used to perform value split action.
using SplitArgTy = std::function<void(ArrayRef<Register>, Register, LLT, LLT, int)>;
MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
MachinePointerInfo &MPO) {
MachineFunction &MF = MIRBuilder.getMF();
- unsigned Alignment = inferAlignmentFromPtrInfo(MF, MPO);
- auto MMO = MF.getMachineMemOperand(
- MPO, MachineMemOperand::MOLoad, Size, Alignment);
+ auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size,
+ inferAlignFromPtrInfo(MF, MPO));
return MIRBuilder.buildLoad(Res, Addr, *MMO);
}
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);
- unsigned Alignment = inferAlignmentFromPtrInfo(MF, MPO);
- auto MMO =
- MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore,
- VA.getLocVT().getStoreSize(), Align(Alignment));
+ auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore,
+ VA.getLocVT().getStoreSize(),
+ inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildStore(ExtReg, Addr, *MMO);
}
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
- unsigned Align = inferAlignmentFromPtrInfo(MF, MPO);
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
- Align);
+ inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}