drm/amd/display: fix clk_mgr naming
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Wed, 20 Mar 2019 21:10:41 +0000 (17:10 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 10 Apr 2019 18:53:27 +0000 (13:53 -0500)
clk_mgr is called dccg in dc_state, this change fixes that

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link.c
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/inc/core_types.h

index abf611538153758280b8d75e133c1ebc30cb9121..71a4dd63c4dc82e3dd8a9528bbe6e0ede85c8f7e 100644 (file)
@@ -1399,7 +1399,7 @@ static enum dc_status enable_link_dp(
 
        pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
                        link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
-       state->dccg->funcs->update_clocks(state->dccg, state, false);
+       state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
 
        dp_enable_link_phy(
                link,
index d0ed95eda508c79898e8a642ff24e2ea405c5699..f798fc28fb2a0d16e0d90a294f9208b81d72c6ec 100644 (file)
@@ -2064,7 +2064,7 @@ void dc_resource_state_construct(
                const struct dc *dc,
                struct dc_state *dst_ctx)
 {
-       dst_ctx->dccg = dc->res_pool->clk_mgr;
+       dst_ctx->clk_mgr = dc->res_pool->clk_mgr;
 }
 
 /**
index a1c4d26c674763c79228cd433f4d56dc9cc5289a..7ac50ab1b7620804b6e59063efbc288f19b96bcb 100644 (file)
@@ -1166,8 +1166,8 @@ static void build_audio_output(
        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
                        pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
                audio_output->pll_info.dp_dto_source_clock_in_khz =
-                               state->dccg->funcs->get_dp_ref_clk_frequency(
-                                               state->dccg);
+                               state->clk_mgr->funcs->get_dp_ref_clk_frequency(
+                                               state->clk_mgr);
        }
 
        audio_output->pll_info.feed_back_divider =
index c3f820cc8287cff7336c23bc5fc6d301e9f78b10..827541e34ee2a97343cd08dd9f6975fd2382e7b4 100644 (file)
@@ -301,7 +301,7 @@ struct dc_state {
        struct dcn_bw_internal_vars dcn_bw_vars;
 #endif
 
-       struct clk_mgr *dccg;
+       struct clk_mgr *clk_mgr;
 
        struct {
                bool full_update_needed : 1;