arm64: dts: mediatek: mt6795: Add tertiary PWM node
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Wed, 12 Apr 2023 11:27:32 +0000 (13:27 +0200)
committerMatthias Brugger <matthias.bgg@gmail.com>
Wed, 12 Apr 2023 12:43:04 +0000 (14:43 +0200)
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is
not display specific and can be used as a generic PWM controller.

This node is left disabled as usage is board-specific.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230412112739.160376-21-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt6795.dtsi

index 090400d..17019fb 100644 (file)
                        status = "disabled";
                };
 
+               pwm2: pwm@11006000 {
+                       compatible = "mediatek,mt6795-pwm";
+                       reg = <0 0x11006000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                                <&pericfg CLK_PERI_PWM>,
+                                <&pericfg CLK_PERI_PWM1>,
+                                <&pericfg CLK_PERI_PWM2>,
+                                <&pericfg CLK_PERI_PWM3>,
+                                <&pericfg CLK_PERI_PWM4>,
+                                <&pericfg CLK_PERI_PWM5>,
+                                <&pericfg CLK_PERI_PWM6>,
+                                <&pericfg CLK_PERI_PWM7>;
+                       clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
+                                     "pwm4", "pwm5", "pwm6", "pwm7";
+                       status = "disabled";
+               };
+
                i2c0: i2c@11007000 {
                        compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
                        reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;