ARM: dts: r8a7745: Add IPMMU DT nodes

Add the six IPMMU instances found in the r8a7745 to DT with a disabled
status.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 9c8d72c..413288b 100644 (file)
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -288,6 +288,64 @@
                        resets = <&cpg 407>;
                };
 
+               ipmmu_sy0: mmu@e6280000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xe6280000 0 0x1000>;
+                       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
+               ipmmu_sy1: mmu@e6290000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xe6290000 0 0x1000>;
+                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
+               ipmmu_ds: mmu@e6740000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xe6740000 0 0x1000>;
+                       interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
+               ipmmu_mp: mmu@ec680000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xec680000 0 0x1000>;
+                       interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
+               ipmmu_mx: mmu@fe951000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xfe951000 0 0x1000>;
+                       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
+               ipmmu_gp: mmu@e62a0000 {
+                       compatible = "renesas,ipmmu-r8a7745",
+                                    "renesas,ipmmu-vmsa";
+                       reg = <0 0xe62a0000 0 0x1000>;
+                       interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                       #iommu-cells = <1>;
+                       status = "disabled";
+               };
+
                icram0: sram@e63a0000 {
                        compatible = "mmio-sram";
                        reg = <0 0xe63a0000 0 0x12000>;