bus@1f059000 {
compatible = "baikal,bt1-apb", "simple-bus";
- reg = <0 0x1f059000 0 0x1000>,
- <0 0x1d000000 0 0x2040000>;
+ reg = <0x1f059000 0x1000>,
+ <0x1d000000 0x2040000>;
reg-names = "ehb", "nodev";
#address-cells = <1>;
#size-cells = <1>;
bus@1f05a000 {
compatible = "baikal,bt1-axi", "simple-bus";
- reg = <0 0x1f05a000 0 0x1000>,
- <0 0x1f04d110 0 0x8>;
+ reg = <0x1f05a000 0x1000>,
+ <0x1f04d110 0x8>;
reg-names = "qos", "ehb";
#address-cells = <1>;
#size-cells = <1>;
#include <dt-bindings/power/rk3288-power.h>
vopb: vopb@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>,
- <0x0 0xff931000 0x0 0x1000>;
+ reg = <0xff930000 0x19c>,
+ <0xff931000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>,
<&cru DCLK_VOP0>,
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox: mailbox@400a0000 {
compatible = "sprd,sc9860-mailbox";
- reg = <0 0x400a0000 0 0x8000>, <0 0x400a8000 0 0x8000>;
+ reg = <0x400a0000 0x8000>, <0x400a8000 0x8000>;
#mbox-cells = <1>;
clock-names = "enable";
clocks = <&aon_gate 53>;
vdec: video-codec@ff660000 {
compatible = "rockchip,rk3399-vdec";
- reg = <0x0 0xff660000 0x0 0x400>;
+ reg = <0xff660000 0x400>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
- reg = <0x0 0xff9a0000 0x0 0x800>;
+ reg = <0xff9a0000 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
- |
nfc: nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
- reg = <0x0 0xff100000 0x0 0x1000>;
+ reg = <0xff100000 0x1000>;
clock-names = "controller", "bus";
clocks = <&clk200>, <&clk100>;
interrupt-parent = <&gic>;
cpts@310d0000 {
compatible = "ti,am65-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
+ reg = <0x310d0000 0x400>;
reg-names = "cpts";
clocks = <&main_cpts_mux>;
clock-names = "cpts";
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
phy@88e2000 {
compatible = "qcom,sm8150-usb-hs-phy";
- reg = <0 0x088e2000 0 0x400>;
+ reg = <0x088e2000 0x400>;
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
easrc: easrc@300c0000 {
compatible = "fsl,imx8mn-easrc";
- reg = <0x0 0x300c0000 0x0 0x10000>;
+ reg = <0x300c0000 0x10000>;
interrupts = <0x0 122 0x4>;
clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
clock-names = "mem";