rtw89: pci: add LTR setting for v1 chip
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 25 Mar 2022 06:00:43 +0000 (14:00 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 6 Apr 2022 08:55:13 +0000 (11:55 +0300)
Add LTR handle to PCI deinit as well.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/pci.c
drivers/net/wireless/realtek/rtw89/pci.h
drivers/net/wireless/realtek/rtw89/reg.h
drivers/net/wireless/realtek/rtw89/rtw8852ae.c
drivers/net/wireless/realtek/rtw89/rtw8852ce.c

index 43bb449..2fd746d 100644 (file)
@@ -2182,10 +2182,13 @@ static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev)
 
 static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev)
 {
+       const struct rtw89_pci_info *info = rtwdev->pci_info;
+
        if (rtwdev->chip->chip_id == RTL8852A) {
                /* ltr sw trigger */
                rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE);
        }
+       info->ltr_set(rtwdev, false);
        rtw89_pci_ctrl_dma_all(rtwdev, false);
        rtw89_pci_clr_idx_all(rtwdev);
 
@@ -2260,10 +2263,13 @@ static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)
        return 0;
 }
 
-static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev)
+int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en)
 {
        u32 val;
 
+       if (!en)
+               return 0;
+
        val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0);
        if (rtw89_pci_ltr_is_err_reg_val(val))
                return -EINVAL;
@@ -2290,13 +2296,61 @@ static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev)
 
        return 0;
 }
+EXPORT_SYMBOL(rtw89_pci_ltr_set);
+
+int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en)
+{
+       u32 dec_ctrl;
+       u32 val32;
+
+       val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0);
+       if (rtw89_pci_ltr_is_err_reg_val(val32))
+               return -EINVAL;
+       val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1);
+       if (rtw89_pci_ltr_is_err_reg_val(val32))
+               return -EINVAL;
+       dec_ctrl = rtw89_read32(rtwdev, R_AX_LTR_DEC_CTRL);
+       if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl))
+               return -EINVAL;
+       val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX3);
+       if (rtw89_pci_ltr_is_err_reg_val(val32))
+               return -EINVAL;
+       val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX0);
+       if (rtw89_pci_ltr_is_err_reg_val(val32))
+               return -EINVAL;
+
+       if (!en) {
+               dec_ctrl &= ~(LTR_EN_BITS | B_AX_LTR_IDX_DRV_MASK | B_AX_LTR_HW_DEC_EN);
+               dec_ctrl |= FIELD_PREP(B_AX_LTR_IDX_DRV_MASK, PCIE_LTR_IDX_IDLE) |
+                           B_AX_LTR_REQ_DRV;
+       } else {
+               dec_ctrl |= B_AX_LTR_HW_DEC_EN;
+       }
+
+       dec_ctrl &= ~B_AX_LTR_SPACE_IDX_V1_MASK;
+       dec_ctrl |= FIELD_PREP(B_AX_LTR_SPACE_IDX_V1_MASK, PCI_LTR_SPC_500US);
+
+       if (en)
+               rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0,
+                                 B_AX_LTR_WD_NOEMP_CHK_V1 | B_AX_LTR_HW_EN);
+       rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK,
+                          PCI_LTR_IDLE_TIMER_3_2MS);
+       rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28);
+       rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28);
+       rtw89_write32(rtwdev, R_AX_LTR_DEC_CTRL, dec_ctrl);
+       rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX3, 0x90039003);
+       rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX0, 0x880b880b);
+
+       return 0;
+}
+EXPORT_SYMBOL(rtw89_pci_ltr_set_v1);
 
 static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev)
 {
        const struct rtw89_pci_info *info = rtwdev->pci_info;
        int ret;
 
-       ret = rtw89_pci_ltr_set(rtwdev);
+       ret = info->ltr_set(rtwdev, true);
        if (ret) {
                rtw89_err(rtwdev, "pci ltr set fail\n");
                return ret;
index 2e86952..99f0cd2 100644 (file)
@@ -647,6 +647,7 @@ struct rtw89_pci_info {
 
        const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
 
+       int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
        u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
                                void *txaddr_info_addr, u32 total_len,
                                dma_addr_t dma, u8 *add_info_nr);
@@ -912,6 +913,8 @@ struct pci_device_id;
 
 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
 void rtw89_pci_remove(struct pci_dev *pdev);
+int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
+int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
                               void *txaddr_info_addr, u32 total_len,
                               dma_addr_t dma, u8 *add_info_nr);
index 6cda6dc..21a4512 100644 (file)
 #define B_AX_RPQ_BUSY BIT(1)
 #define B_AX_RXQ_BUSY BIT(0)
 
+#define R_AX_LTR_DEC_CTRL 0x1600
+#define B_AX_LTR_IDX_DRV_VLD BIT(16)
+#define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14)
+#define B_AX_LTR_IDX_FW_VLD BIT(13)
+#define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11)
+#define B_AX_LTR_IDX_HW_VLD BIT(10)
+#define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
+#define B_AX_LTR_REQ_DRV BIT(7)
+#define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5)
+#define PCIE_LTR_IDX_IDLE 3
+#define B_AX_LTR_DRV_DEC_EN BIT(4)
+#define B_AX_LTR_FW_DEC_EN BIT(3)
+#define B_AX_LTR_HW_DEC_EN BIT(2)
+#define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0)
+#define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN)
+
+#define R_AX_LTR_LATENCY_IDX0 0x1604
+#define R_AX_LTR_LATENCY_IDX1 0x1608
+#define R_AX_LTR_LATENCY_IDX2 0x160C
+#define R_AX_LTR_LATENCY_IDX3 0x1610
+
 #define R_AX_HCI_FC_CTRL_V1 0x1700
 #define R_AX_CH_PAGE_CTRL_V1 0x1704
 
 #define B_AX_APP_LTR_ACT BIT(5)
 #define B_AX_APP_LTR_IDLE BIT(4)
 #define B_AX_LTR_EN BIT(1)
+#define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1)
 #define B_AX_LTR_HW_EN BIT(0)
 
 #define R_AX_LTR_CTRL_1 0x8414
index 6055e8b..61a1693 100644 (file)
@@ -40,6 +40,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
 
        .dma_addr_set           = &rtw89_pci_ch_dma_addr_set,
 
+       .ltr_set                = rtw89_pci_ltr_set,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info,
 };
 
index dca023e..aeafac5 100644 (file)
@@ -41,6 +41,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
 
        .dma_addr_set           = &rtw89_pci_ch_dma_addr_set_v1,
 
+       .ltr_set                = rtw89_pci_ltr_set_v1,
        .fill_txaddr_info       = rtw89_pci_fill_txaddr_info_v1,
 };