dt-bindings: reset: Add StarFive JH7110 system reset definitions

Add resets for the StarFive JH7110 system reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

diff --git a/include/dt-bindings/reset/starfive-jh7110-sys.h b/include/dt-bindings/reset/starfive-jh7110-sys.h
new file mode 100644 (file)
index 0000000..eb56b56
--- /dev/null
+++ b/include/dt-bindings/reset/starfive-jh7110-sys.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_SYS_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_SYS_H__
+
+#define JH7110_SYSRST_JTAG2APB                   0 /* rstn_u0_jtag2apb_presetn */
+#define JH7110_SYSRST_SYSCON                     1 /* rstn_u0_sys_syscon_presetn */
+#define JH7110_SYSRST_IOMUX                      2 /* rstn_u0_sys_iomux_presetn */
+#define JH7110_SYSRST_BUS                        3 /* rst_u0_u7mc_sft7110_rst_bus */
+#define JH7110_SYSRST_DEBUG                      4 /* rst_u0_u7mc_sft7110_debug_reset */
+#define JH7110_SYSRST_CORE0                      5 /* rst_u0_u7mc_sft7110_rst_core0 */
+#define JH7110_SYSRST_CORE1                      6 /* rst_u0_u7mc_sft7110_rst_core1 */
+#define JH7110_SYSRST_CORE2                      7 /* rst_u0_u7mc_sft7110_rst_core2 */
+#define JH7110_SYSRST_CORE3                      8 /* rst_u0_u7mc_sft7110_rst_core3 */
+#define JH7110_SYSRST_CORE4                      9 /* rst_u0_u7mc_sft7110_rst_core4 */
+#define JH7110_SYSRST_CORE0_ST                  10 /* rst_u0_u7mc_sft7110_rst_core0_st */
+#define JH7110_SYSRST_CORE1_ST                  11 /* rst_u0_u7mc_sft7110_rst_core1_st */
+#define JH7110_SYSRST_CORE2_ST                  12 /* rst_u0_u7mc_sft7110_rst_core2_st */
+#define JH7110_SYSRST_CORE3_ST                  13 /* rst_u0_u7mc_sft7110_rst_core3_st */
+#define JH7110_SYSRST_CORE4_ST                  14 /* rst_u0_u7mc_sft7110_rst_core4_st */
+#define JH7110_SYSRST_TRACE0                    15 /* rst_u0_u7mc_sft7110_trace_rst0 */
+#define JH7110_SYSRST_TRACE1                    16 /* rst_u0_u7mc_sft7110_trace_rst1 */
+#define JH7110_SYSRST_TRACE2                    17 /* rst_u0_u7mc_sft7110_trace_rst2 */
+#define JH7110_SYSRST_TRACE3                    18 /* rst_u0_u7mc_sft7110_trace_rst3 */
+#define JH7110_SYSRST_TRACE4                    19 /* rst_u0_u7mc_sft7110_trace_rst4 */
+#define JH7110_SYSRST_TRACE_COM                         20 /* rst_u0_u7mc_sft7110_trace_com_rst */
+#define JH7110_SYSRST_GPU_APB                   21 /* rstn_u0_img_gpu_rstn_apb */
+#define JH7110_SYSRST_GPU_DOMA                  22 /* rstn_u0_img_gpu_rstn_doma */
+#define JH7110_SYSRST_NOC_BUS_APB_BUS           23 /* rstn_u0_sft7110_noc_bus_reset_apb_bus_n */
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI       24 /* rstn_u0_sft7110_noc_bus_reset_axicfg0_axi_n */
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI           25 /* rstn_u0_sft7110_noc_bus_reset_cpu_axi_n */
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI          26 /* rstn_u0_sft7110_noc_bus_reset_disp_axi_n */
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI           27 /* rstn_u0_sft7110_noc_bus_reset_gpu_axi_n */
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI           28 /* rstn_u0_sft7110_noc_bus_reset_isp_axi_n */
+#define JH7110_SYSRST_NOC_BUS_DDRC              29 /* rstn_u0_sft7110_noc_bus_reset_ddrc_n */
+#define JH7110_SYSRST_NOC_BUS_STG_AXI           30 /* rstn_u0_sft7110_noc_bus_reset_stg_axi_n */
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI          31 /* rstn_u0_sft7110_noc_bus_reset_vdec_axi_n */
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI          32 /* rstn_u0_sft7110_noc_bus_reset_venc_axi_n */
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB          33 /* rstn_u0_axi_cfg1_dec_rstn_ahb */
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN                 34 /* rstn_u0_axi_cfg1_dec_rstn_main */
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN                 35 /* rstn_u0_axi_cfg0_dec_rstn_main */
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV     36 /* rstn_u0_axi_cfg0_dec_rstn_main_div */
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4        37 /* rstn_u0_axi_cfg0_dec_rstn_hifi4 */
+#define JH7110_SYSRST_DDR_AXI                   38 /* rstn_u0_ddr_sft7110_rst_axi */
+#define JH7110_SYSRST_DDR_OSC                   39 /* rstn_u0_ddr_sft7110_rst_osc */
+#define JH7110_SYSRST_DDR_APB                   40 /* rstn_u0_ddr_sft7110_rst_apb */
+#define JH7110_SYSRST_DOM_ISP_TOP_N             41 /* rstn_u0_dom_isp_top_rstn_ip_top_reset_n */
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI           42 /* rstn_u0_dom_isp_top_rstn_isp_axi */
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC          43 /* rstn_u0_dom_vout_top_rstn_vout_src */
+#define JH7110_SYSRST_CODAJ12_AXI               44 /* rstn_u0_CODAJ12_rstn_axi */
+#define JH7110_SYSRST_CODAJ12_CORE              45 /* rstn_u0_CODAJ12_rstn_core */
+#define JH7110_SYSRST_CODAJ12_APB               46 /* rstn_u0_CODAJ12_rstn_apb */
+#define JH7110_SYSRST_WAVE511_AXI               47 /* rstn_u0_WAVE511_rstn_axi */
+#define JH7110_SYSRST_WAVE511_BPU               48 /* rstn_u0_WAVE511_rstn_bpu */
+#define JH7110_SYSRST_WAVE511_VCE               49 /* rstn_u0_WAVE511_rstn_vce */
+#define JH7110_SYSRST_WAVE511_APB               50 /* rstn_u0_WAVE511_rstn_apb */
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG          51 /* rstn_u0_vdec_jpg_arb_jpgresetn */
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN                 52 /* rstn_u0_vdec_jpg_arb_mainresetn */
+#define JH7110_SYSRST_AXIMEM0_AXI               53 /* rstn_u0_aximem_128b_rstn_axi */
+#define JH7110_SYSRST_WAVE420L_AXI              54 /* rstn_u0_wave420l_rstn_axi */
+#define JH7110_SYSRST_WAVE420L_BPU              55 /* rstn_u0_wave420l_rstn_bpu */
+#define JH7110_SYSRST_WAVE420L_VCE              56 /* rstn_u0_wave420l_rstn_vce */
+#define JH7110_SYSRST_WAVE420L_APB              57 /* rstn_u0_wave420l_rstn_apb */
+#define JH7110_SYSRST_AXIMEM1_AXI               58 /* rstn_u1_aximem_128b_rstn_axi */
+#define JH7110_SYSRST_AXIMEM2_AXI               59 /* rstn_u2_aximem_128b_rstn_axi */
+#define JH7110_SYSRST_INTMEM                    60 /* rstn_u0_intmem_rom_sram_rstn_rom */
+#define JH7110_SYSRST_QSPI_AHB                  61 /* rstn_u0_cdns_qspi_rstn_ahb */
+#define JH7110_SYSRST_QSPI_APB                  62 /* rstn_u0_cdns_qspi_rstn_abb */
+#define JH7110_SYSRST_QSPI_REF                  63 /* rstn_u0_cdns_qspi_rstn_ref */
+
+#define JH7110_SYSRST_SDIO0_AHB                         64 /* rstn_u0_dw_sdio_rstn_ahb */
+#define JH7110_SYSRST_SDIO1_AHB                         65 /* rstn_u1_dw_sdio_rstn_ahb */
+#define JH7110_SYSRST_GMAC1_AXI                         66 /* rstn_u1_dw_gmac5_axi64_aresetn_i */
+#define JH7110_SYSRST_GMAC1_AHB                         67 /* rstn_u1_dw_gmac5_axi64_hreset_n */
+#define JH7110_SYSRST_MAILBOX                   68 /* rstn_u0_mailbox_presetn */
+#define JH7110_SYSRST_SPI0_APB                  69 /* rstn_u0_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI1_APB                  70 /* rstn_u1_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI2_APB                  71 /* rstn_u2_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI3_APB                  72 /* rstn_u3_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI4_APB                  73 /* rstn_u4_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI5_APB                  74 /* rstn_u5_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_SPI6_APB                  75 /* rstn_u6_ssp_spi_rstn_apb */
+#define JH7110_SYSRST_I2C0_APB                  76 /* rstn_u0_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C1_APB                  77 /* rstn_u1_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C2_APB                  78 /* rstn_u2_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C3_APB                  79 /* rstn_u3_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C4_APB                  80 /* rstn_u4_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C5_APB                  81 /* rstn_u5_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_I2C6_APB                  82 /* rstn_u6_dw_i2c_rstn_apb */
+#define JH7110_SYSRST_UART0_APB                         83 /* rstn_u0_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART0_CORE                84 /* rstn_u0_dw_uart_rstn_core */
+#define JH7110_SYSRST_UART1_APB                         85 /* rstn_u1_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART1_CORE                86 /* rstn_u1_dw_uart_rstn_core */
+#define JH7110_SYSRST_UART2_APB                         87 /* rstn_u2_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART2_CORE                88 /* rstn_u2_dw_uart_rstn_core */
+#define JH7110_SYSRST_UART3_APB                         89 /* rstn_u3_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART3_CORE                90 /* rstn_u3_dw_uart_rstn_core */
+#define JH7110_SYSRST_UART4_APB                         91 /* rstn_u4_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART4_CORE                92 /* rstn_u4_dw_uart_rstn_core */
+#define JH7110_SYSRST_UART5_APB                         93 /* rstn_u5_dw_uart_rstn_apb */
+#define JH7110_SYSRST_UART5_CORE                94 /* rstn_u5_dw_uart_rstn_core */
+#define JH7110_SYSRST_SPDIF_APB                         95 /* rstn_u0_cdns_spdif_rstn_apb */
+
+#define JH7110_SYSRST_PWMDAC_APB                96 /* rstn_u0_pwmdac_rstn_apb */
+#define JH7110_SYSRST_PDM_DMIC                  97 /* rstn_u0_pdm_4mic_rstn_dmic */
+#define JH7110_SYSRST_PDM_APB                   98 /* rstn_u0_pdm_4mic_rstn_apb */
+#define JH7110_SYSRST_I2SRX_APB                         99 /* rstn_u0_i2srx_3ch_rstn_apb */
+#define JH7110_SYSRST_I2SRX_BCLK               100 /* rstn_u0_i2srx_3ch_rstn_bclk */
+#define JH7110_SYSRST_I2STX0_APB               101 /* rstn_u0_i2stx_4ch_rstn_apb */
+#define JH7110_SYSRST_I2STX0_BCLK              102 /* rstn_u0_i2stx_4ch_rstn_bclk */
+#define JH7110_SYSRST_I2STX1_APB               103 /* rstn_u0_i2stx_4ch_rstn_apb */
+#define JH7110_SYSRST_I2STX1_BCLK              104 /* rstn_u0_i2stx_4ch_rstn_bclk */
+#define JH7110_SYSRST_TDM_AHB                  105 /* rstn_u0_tdm16slot_rstn_ahb */
+#define JH7110_SYSRST_TDM_CORE                 106 /* rstn_u0_tdm16slot_rstn_tdm */
+#define JH7110_SYSRST_TDM_APB                  107 /* rstn_u0_tdm16slot_rstn_apb */
+#define JH7110_SYSRST_PWM_APB                  108 /* rstn_u0_pwm_8ch_rstn_apb */
+#define JH7110_SYSRST_WDT_APB                  109 /* rstn_u0_dskit_wdt_rstn_apb */
+#define JH7110_SYSRST_WDT_CORE                 110 /* rstn_u0_dskit_wdt_rstn_wdt */
+#define JH7110_SYSRST_CAN0_APB                 111 /* rstn_u0_can_ctrl_rstn_apb */
+#define JH7110_SYSRST_CAN0_CORE                        112 /* rstn_u0_can_ctrl_rstn_can */
+#define JH7110_SYSRST_CAN0_TIMER               113 /* rstn_u0_can_ctrl_rstn_timer */
+#define JH7110_SYSRST_CAN1_APB                 114 /* rstn_u1_can_ctrl_rstn_apb */
+#define JH7110_SYSRST_CAN1_CORE                        115 /* rstn_u1_can_ctrl_rstn_can */
+#define JH7110_SYSRST_CAN1_TIMER               116 /* rstn_u1_can_ctrl_rstn_timer */
+#define JH7110_SYSRST_TIMER_APB                        117 /* rstn_u0_si5_timer_rstn_apb */
+#define JH7110_SYSRST_TIMER0                   118 /* rstn_u0_si5_timer_rstn_timer0 */
+#define JH7110_SYSRST_TIMER1                   119 /* rstn_u0_si5_timer_rstn_timer1 */
+#define JH7110_SYSRST_TIMER2                   120 /* rstn_u0_si5_timer_rstn_timer2 */
+#define JH7110_SYSRST_TIMER3                   121 /* rstn_u0_si5_timer_rstn_timer3 */
+#define JH7110_SYSRST_INT_CTRL_APB             122 /* rstn_u0_int_ctrl_rstn_apb */
+#define JH7110_SYSRST_TEMP_APB                 123 /* rstn_u0_temp_sensor_rstn_apb */
+#define JH7110_SYSRST_TEMP_CORE                        124 /* rstn_u0_temp_sensor_rstn_temp */
+#define JH7110_SYSRST_JTAG_CERTIFICATION       125 /* rstn_u0_jtag_certification_rst_n */
+
+#define        JH7110_SYSRST_END                       126
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_SYS_H__ */