static const struct resources csiphy_res_8x16[] = {
/* CSIPHY0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
.clock_rate = { { 0 },
{ 0 },
/* CSIPHY1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
.clock_rate = { { 0 },
{ 0 },
static const struct resources csid_res_8x16[] = {
/* CSID0 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
"csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
.clock_rate = { { 0 },
/* CSID1 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
"csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
.clock_rate = { { 0 },
static const struct resources vfe_res_8x16[] = {
/* VFE0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "vfe0", "csi_vfe0",
"vfe_ahb", "vfe_axi", "ahb" },
.clock_rate = { { 0 },
static const struct resources csiphy_res_8x96[] = {
/* CSIPHY0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
.clock_rate = { { 0 },
{ 0 },
/* CSIPHY1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
.clock_rate = { { 0 },
{ 0 },
/* CSIPHY2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
.clock_rate = { { 0 },
{ 0 },
static const struct resources csid_res_8x96[] = {
/* CSID0 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
"csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
.clock_rate = { { 0 },
/* CSID1 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
"csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
.clock_rate = { { 0 },
/* CSID2 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
"csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
.clock_rate = { { 0 },
/* CSID3 */
{
- .regulator = { "vdda" },
+ .regulators = { "vdda" },
.clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
"csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
.clock_rate = { { 0 },
static const struct resources vfe_res_8x96[] = {
/* VFE0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
"vfe0_ahb", "vfe_axi", "vfe0_stream"},
.clock_rate = { { 0 },
/* VFE1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
"vfe1_ahb", "vfe_axi", "vfe1_stream"},
.clock_rate = { { 0 },
static const struct resources csiphy_res_660[] = {
/* CSIPHY0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer",
"csi0_phy", "csiphy_ahb2crif" },
.clock_rate = { { 0 },
/* CSIPHY1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer",
"csi1_phy", "csiphy_ahb2crif" },
.clock_rate = { { 0 },
/* CSIPHY2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer",
"csi2_phy", "csiphy_ahb2crif" },
.clock_rate = { { 0 },
static const struct resources csid_res_660[] = {
/* CSID0 */
{
- .regulator = { "vdda", "vdd_sec" },
+ .regulators = { "vdda", "vdd_sec" },
.clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
"csi0", "csi0_phy", "csi0_pix", "csi0_rdi",
"cphy_csid0" },
/* CSID1 */
{
- .regulator = { "vdda", "vdd_sec" },
+ .regulators = { "vdda", "vdd_sec" },
.clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
"csi1", "csi1_phy", "csi1_pix", "csi1_rdi",
"cphy_csid1" },
/* CSID2 */
{
- .regulator = { "vdda", "vdd_sec" },
+ .regulators = { "vdda", "vdd_sec" },
.clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
"csi2", "csi2_phy", "csi2_pix", "csi2_rdi",
"cphy_csid2" },
/* CSID3 */
{
- .regulator = { "vdda", "vdd_sec" },
+ .regulators = { "vdda", "vdd_sec" },
.clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
"csi3", "csi3_phy", "csi3_pix", "csi3_rdi",
"cphy_csid3" },
static const struct resources vfe_res_660[] = {
/* VFE0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "throttle_axi", "top_ahb", "ahb", "vfe0",
"csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi",
"vfe0_stream"},
/* VFE1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "throttle_axi", "top_ahb", "ahb", "vfe1",
"csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi",
"vfe1_stream"},
static const struct resources csiphy_res_845[] = {
/* CSIPHY0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
"cpas_ahb", "cphy_rx_src", "csiphy0",
"csiphy0_timer_src", "csiphy0_timer" },
/* CSIPHY1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
"cpas_ahb", "cphy_rx_src", "csiphy1",
"csiphy1_timer_src", "csiphy1_timer" },
/* CSIPHY2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
"cpas_ahb", "cphy_rx_src", "csiphy2",
"csiphy2_timer_src", "csiphy2_timer" },
/* CSIPHY3 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src",
"cpas_ahb", "cphy_rx_src", "csiphy3",
"csiphy3_timer_src", "csiphy3_timer" },
static const struct resources csid_res_845[] = {
/* CSID0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
"soc_ahb", "vfe0", "vfe0_src",
"vfe0_cphy_rx", "csi0",
/* CSID1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
"soc_ahb", "vfe1", "vfe1_src",
"vfe1_cphy_rx", "csi1",
/* CSID2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src",
"soc_ahb", "vfe_lite", "vfe_lite_src",
"vfe_lite_cphy_rx", "csi2",
static const struct resources vfe_res_845[] = {
/* VFE0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
"soc_ahb", "vfe0", "vfe0_axi",
"vfe0_src", "csi0",
/* VFE1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
"soc_ahb", "vfe1", "vfe1_axi",
"vfe1_src", "csi1",
/* VFE-lite */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src",
"soc_ahb", "vfe_lite",
"vfe_lite_src", "csi2",
static const struct resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy0", "csiphy0_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
},
/* CSIPHY1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy1", "csiphy1_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
},
/* CSIPHY2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy2", "csiphy2_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
},
/* CSIPHY3 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy3", "csiphy3_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
},
/* CSIPHY4 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy4", "csiphy4_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
},
/* CSIPHY5 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "csiphy5", "csiphy5_timer" },
.clock_rate = { { 400000000 },
{ 300000000 } },
static const struct resources csid_res_8250[] = {
/* CSID0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" },
.clock_rate = { { 400000000 },
{ 400000000 },
},
/* CSID1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" },
.clock_rate = { { 400000000 },
{ 400000000 },
},
/* CSID2 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
.clock_rate = { { 400000000 },
{ 400000000 },
},
/* CSID3 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" },
.clock_rate = { { 400000000 },
{ 400000000 },
static const struct resources vfe_res_8250[] = {
/* VFE0 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
"camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0",
"vfe0_axi", "cam_hf_axi" },
},
/* VFE1 */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
"camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1",
"vfe1_axi", "cam_hf_axi" },
},
/* VFE2 (lite) */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
"camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
"vfe_lite", "cam_hf_axi" },
},
/* VFE3 (lite) */
{
- .regulator = { NULL },
+ .regulators = { NULL },
.clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb",
"camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi",
"vfe_lite", "cam_hf_axi" },