mx7dsabre: Enable DM_ETH
authorJoris Offouga <offougajoris@gmail.com>
Sun, 8 Dec 2019 17:02:30 +0000 (18:02 +0100)
committerStefano Babic <sbabic@denx.de>
Tue, 7 Jan 2020 09:26:56 +0000 (10:26 +0100)
Also sync device tree with v5.5-rc1
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
arch/arm/dts/imx7d-sdb-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/imx7d-sdb.dts
board/freescale/mx7dsabresd/mx7dsabresd.c
configs/mx7dsabresd_defconfig
configs/mx7dsabresd_qspi_defconfig
include/configs/mx7dsabresd.h

diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
new file mode 100644 (file)
index 0000000..05dd74e
--- /dev/null
@@ -0,0 +1,3 @@
+&fec2 {
+       status = "disable";
+};
index 76aa69a..8191ac7 100644 (file)
        model = "Freescale i.MX7 SabreSD Board";
        compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
-       aliases {
-               spi5 = &soft_spi;
+       chosen {
+               stdout-path = &uart1;
        };
 
-       memory {
+       memory@80000000 {
+               device_type = "memory";
                reg = <0x80000000 0x80000000>;
        };
 
-       soft_spi: soft-spi {
+       gpio-keys {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_keys>;
+
+               volume-up {
+                       label = "Volume Up";
+                       gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_VOLUMEUP>;
+                       wakeup-source;
+               };
+
+               volume-down {
+                       label = "Volume Down";
+                       gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+                       linux,code = <KEY_VOLUMEDOWN>;
+                       wakeup-source;
+               };
+       };
+
+       spi4 {
                compatible = "spi-gpio";
                pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_spi1>;
-               status = "okay";
-               gpio-sck = <&gpio1 13 0>;
-               gpio-mosi = <&gpio1 9 0>;
-               cs-gpios = <&gpio1 12 0>;
+               pinctrl-0 = <&pinctrl_spi4>;
+               gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>;
+               gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>;
+               cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
                num-chipselects = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
 
-               gpio_spi: gpio_spi@0 {
+               extended_io: gpio-expander@0 {
                        compatible = "fairchild,74hc595";
                        gpio-controller;
                        #gpio-cells = <2>;
                        reg = <0>;
                        registers-number = <1>;
-                       registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
                        spi-max-frequency = <100000>;
                };
        };
 
-       regulators {
-               compatible = "simple-bus";
-               #address-cells = <1>;
-               #size-cells = <0>;
+       reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb_otg1_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
 
-               reg_usb_otg1_vbus: regulator@0 {
-                       compatible = "regulator-fixed";
-                       reg = <0>;
-                       regulator-name = "usb_otg1_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
-                       enable-active-high;
-               };
+       reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+               compatible = "regulator-fixed";
+               regulator-name = "usb_otg2_vbus";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
 
-               reg_usb_otg2_vbus: regulator@1 {
-                       compatible = "regulator-fixed";
-                       reg = <1>;
-                       regulator-name = "usb_otg2_vbus";
-                       regulator-min-microvolt = <5000000>;
-                       regulator-max-microvolt = <5000000>;
-                       gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
-                       enable-active-high;
-               };
-
-               reg_sd1_vmmc: regulator@3 {
-                       compatible = "regulator-fixed";
-                       regulator-name = "VDD_SD1";
-                       regulator-min-microvolt = <3300000>;
-                       regulator-max-microvolt = <3300000>;
-                       gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
-                       startup-delay-us = <200000>;
-                       enable-active-high;
-               };
+       reg_vref_1v8: regulator-vref-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "vref-1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
        };
-};
 
-&iomuxc {
-       imx7d-sdb {
-               pinctrl_spi1: spi1grp {
-                       fsl,pins = <
-                               MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
-                               MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
-                               MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
-                       >;
-               };
+       reg_brcm: regulator-brcm {
+               compatible = "regulator-fixed";
+               gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-name = "brcm_reg";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_brcm_reg>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               startup-delay-us = <200000>;
+       };
 
-               pinctrl_i2c1: i2c1grp {
-                       fsl,pins = <
-                               MX7D_PAD_I2C1_SDA__I2C1_SDA     0x4000007f
-                               MX7D_PAD_I2C1_SCL__I2C1_SCL     0x4000007f
-                       >;
-               };
+       reg_lcd_3v3: regulator-lcd-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "lcd-3v3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
+       };
 
-               pinctrl_i2c2: i2c2grp {
-                       fsl,pins = <
-                               MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
-                               MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
-                       >;
-               };
+       reg_can2_3v3: regulator-can2-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "can2-3v3";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_flexcan2_reg>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
+       };
 
-               pinctrl_i2c3: i2c3grp {
-                       fsl,pins = <
-                               MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
-                               MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
-                       >;
-               };
+       reg_fec2_3v3: regulator-fec2-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "fec2-3v3";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_enet2_reg>;
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
+       };
 
-               pinctrl_i2c4: i2c4grp {
-                       fsl,pins = <
-                               MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
-                               MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
-                       >;
-               };
+       backlight: backlight {
+               compatible = "pwm-backlight";
+               pwms = <&pwm1 0 5000000 0>;
+               brightness-levels = <0 4 8 16 32 64 128 255>;
+               default-brightness-level = <6>;
+               status = "okay";
+       };
 
-               pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
-                       fsl,pins = <
-                               MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
-                               MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
-                               MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
-                               MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x59 /* VSELECT */
-                       >;
-               };
+       panel {
+               compatible = "innolux,at043tn24";
+               backlight = <&backlight>;
+               power-supply = <&reg_lcd_3v3>;
 
-               pinctrl_usdhc1: usdhc1grp {
-                       fsl,pins = <
-                               MX7D_PAD_SD1_CMD__SD1_CMD               0x59
-                               MX7D_PAD_SD1_CLK__SD1_CLK               0x19
-                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
-                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
-                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
-                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
-                       >;
+               port {
+                       panel_in: endpoint {
+                               remote-endpoint = <&display_out>;
+                       };
                };
+       };
+};
 
-               pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD1_CMD__SD1_CMD               0x5a
-                               MX7D_PAD_SD1_CLK__SD1_CLK               0x1a
-                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
-                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
-                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
-                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
-                       >;
-               };
+&adc1 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
 
-               pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD1_CMD__SD1_CMD               0x5b
-                               MX7D_PAD_SD1_CLK__SD1_CLK               0x1b
-                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
-                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
-                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
-                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
-                       >;
-               };
+&adc2 {
+       vref-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
 
-               pinctrl_usdhc2: usdhc2grp {
-                       fsl,pins = <
-                               MX7D_PAD_SD2_CMD__SD2_CMD       0x59
-                               MX7D_PAD_SD2_CLK__SD2_CLK       0x19
-                               MX7D_PAD_SD2_DATA0__SD2_DATA0   0x59
-                               MX7D_PAD_SD2_DATA1__SD2_DATA1   0x59
-                               MX7D_PAD_SD2_DATA2__SD2_DATA2   0x59
-                               MX7D_PAD_SD2_DATA3__SD2_DATA3   0x59
-                               MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x19 /* WL_REG_ON */
-                               MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20        0x19 /* WL_HOST_WAKE */
-                       >;
-               };
+&cpu0 {
+       cpu-supply = <&sw1a_reg>;
+};
 
-               pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
-                               MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
-                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
-                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
-                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
-                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
-                       >;
-               };
+&ecspi3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3>;
+       cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+       status = "okay";
 
-               pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
-                               MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
-                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
-                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
-                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
-                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
-                       >;
-               };
+       tsc2046@0 {
+               compatible = "ti,tsc2046";
+               reg = <0>;
+               spi-max-frequency = <1000000>;
+               pinctrl-names ="default";
+               pinctrl-0 = <&pinctrl_tsc2046_pendown>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <29 0>;
+               pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+               ti,x-min = /bits/ 16 <0>;
+               ti,x-max = /bits/ 16 <0>;
+               ti,y-min = /bits/ 16 <0>;
+               ti,y-max = /bits/ 16 <0>;
+               ti,pressure-max = /bits/ 16 <0>;
+               ti,x-plate-ohms = /bits/ 16 <400>;
+               wakeup-source;
+       };
+};
 
-               pinctrl_usdhc3: usdhc3grp {
-                       fsl,pins = <
-                               MX7D_PAD_SD3_CMD__SD3_CMD               0x59
-                               MX7D_PAD_SD3_CLK__SD3_CLK               0x19
-                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
-                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
-                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
-                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
-                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
-                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
-                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
-                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
-                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
-                       >;
-               };
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet1>;
+       assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <100000000>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
+       status = "okay";
 
-               pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
-                               MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
-                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
-                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
-                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
-                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
-                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
-                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
-                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
-                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
-                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
-                       >;
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       reg = <0>;
                };
 
-               pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
-                       fsl,pins = <
-                               MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
-                               MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
-                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
-                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
-                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
-                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
-                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
-                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
-                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
-                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
-                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
-                       >;
+               ethphy1: ethernet-phy@1 {
+                       reg = <1>;
                };
        };
 };
 
+&fec2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet2>;
+       assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+       assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+       assigned-clock-rates = <0>, <100000000>;
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy1>;
+       phy-supply = <&reg_fec2_3v3>;
+       fsl,magic-packet;
+       status = "okay";
+};
+
+&flexcan2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexcan2>;
+       xceiver-supply = <&reg_can2_3v3>;
+       status = "okay";
+};
+
 &i2c1 {
-       clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
        status = "okay";
 
-       pmic: pfuze3000@08 {
+       pmic: pfuze3000@8 {
                compatible = "fsl,pfuze3000";
                reg = <0x08>;
 
                regulators {
                        sw1a_reg: sw1a {
                                regulator-min-microvolt = <700000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-max-microvolt = <1475000>;
                                regulator-boot-on;
                                regulator-always-on;
                                regulator-ramp-delay = <6250>;
                        };
 
                        sw2_reg: sw2 {
-                               regulator-min-microvolt = <1500000>;
-                               regulator-max-microvolt = <1850000>;
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <1800000>;
                                regulator-boot-on;
                                regulator-always-on;
                        };
                        vgen2_reg: vldo2 {
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <1550000>;
-                               regulator-always-on;
                        };
 
                        vgen3_reg: vccsd {
                        };
 
                        vgen6_reg: vldo4 {
-                               regulator-min-microvolt = <1800000>;
-                               regulator-max-microvolt = <3300000>;
+                               regulator-min-microvolt = <2800000>;
+                               regulator-max-microvolt = <2800000>;
                                regulator-always-on;
                        };
                };
 };
 
 &i2c2 {
-       clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2>;
        status = "okay";
+
+       mpl3115@60 {
+               compatible = "fsl,mpl3115";
+               reg = <0x60>;
+       };
 };
 
 &i2c3 {
-       clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c3>;
        status = "okay";
 };
 
 &i2c4 {
-       clock-frequency = <100000>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c4>;
        status = "okay";
+
+       codec: wm8960@1a {
+               compatible = "wlf,wm8960";
+               reg = <0x1a>;
+               clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+               clock-names = "mclk";
+               wlf,shared-lrclk;
+       };
+};
+
+&lcdif {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_lcdif>;
+       status = "okay";
+
+       port {
+               display_out: endpoint {
+                       remote-endpoint = <&panel_in>;
+               };
+       };
+};
+
+&snvs_pwrkey {
+       status = "okay";
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       status = "okay";
+};
+
+&uart6 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart6>;
+       assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+       assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&usbotg1 {
+       vbus-supply = <&reg_usb_otg1_vbus>;
+       status = "okay";
+};
+
+&usbotg2 {
+       vbus-supply = <&reg_usb_otg2_vbus>;
+       dr_mode = "host";
+       status = "okay";
 };
 
 &usdhc1 {
-       pinctrl-names = "default", "state_100mhz", "state_200mhz";
-       pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
-       pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
-       pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
        cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
        wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-       vmmc-supply = <&reg_sd1_vmmc>;
-       fsl,tuning-start-tap = <20>;
-       fsl,tuning-step= <2>;
+       wakeup-source;
+       keep-power-in-suspend;
        status = "okay";
 };
 
        pinctrl-0 = <&pinctrl_usdhc2>;
        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+       wakeup-source;
+       keep-power-in-suspend;
        non-removable;
-       fsl,tuning-start-tap = <20>;
-       fsl,tuning-step= <2>;
+       vmmc-supply = <&reg_brcm>;
+       fsl,tuning-step = <2>;
        status = "okay";
 };
 
        pinctrl-0 = <&pinctrl_usdhc3>;
        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+       assigned-clock-rates = <400000000>;
        bus-width = <8>;
+       fsl,tuning-step = <2>;
        non-removable;
-       fsl,tuning-start-tap = <20>;
-       fsl,tuning-step= <2>;
        status = "okay";
 };
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+};
+
+&iomuxc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_hog>;
+
+       imx7d-sdb {
+               pinctrl_brcm_reg: brcmreggrp {
+                       fsl,pins = <
+                               MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
+                       >;
+               };
+
+               pinctrl_ecspi3: ecspi3grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
+                               MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
+                               MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
+                               MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
+                       >;
+               };
+
+               pinctrl_enet1: enet1grp {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
+                               MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
+                               MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
+                               MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
+                               MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
+                               MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
+                               MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
+                               MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+                               MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
+                               MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
+                               MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
+                               MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
+                               MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
+                               MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+                       >;
+               };
+
+               pinctrl_enet2: enet2grp {
+                       fsl,pins = <
+                               MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
+                               MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
+                               MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
+                               MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
+                               MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
+                               MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
+                               MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
+                               MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
+                               MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
+                               MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
+                               MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
+                               MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
+                       >;
+               };
+
+               pinctrl_enet2_reg: enet2reggrp {
+                       fsl,pins = <
+                               MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x14
+                       >;
+               };
+
+               pinctrl_flexcan2: flexcan2grp {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
+                               MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
+                       >;
+               };
+
+               pinctrl_flexcan2_reg: flexcan2reggrp {
+                       fsl,pins = <
+                               MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
+                       >;
+               };
+
+               pinctrl_gpio_keys: gpio_keysgrp {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
+                               MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
+                       >;
+               };
+
+               pinctrl_hog: hoggrp {
+                       fsl,pins = <
+                               MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
+                               MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c2: i2c2grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
+                               MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c3: i2c3grp {
+                       fsl,pins = <
+                               MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
+                               MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
+                       >;
+               };
+
+               pinctrl_i2c4: i2c4grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
+                               MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
+                       >;
+               };
+
+               pinctrl_lcdif: lcdifgrp {
+                       fsl,pins = <
+                               MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
+                               MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
+                               MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
+                               MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
+                               MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
+                               MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
+                               MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
+                               MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
+                               MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
+                               MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
+                               MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
+                               MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
+                               MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
+                               MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
+                               MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
+                               MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
+                               MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
+                               MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
+                               MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
+                               MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
+                               MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
+                               MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
+                               MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
+                               MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
+                               MX7D_PAD_LCD_CLK__LCD_CLK               0x79
+                               MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
+                               MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
+                               MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
+                               MX7D_PAD_LCD_RESET__LCD_RESET           0x79
+                       >;
+               };
+
+               pinctrl_spi4: spi4grp {
+                       fsl,pins = <
+                               MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
+                               MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
+                               MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
+                       >;
+               };
+
+               pinctrl_tsc2046_pendown: tsc2046_pendown {
+                       fsl,pins = <
+                               MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
+                               MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
+                       >;
+               };
+
+               pinctrl_uart5: uart5grp {
+                       fsl,pins = <
+                               MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
+                               MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
+                               MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
+                               MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
+                       >;
+               };
+
+               pinctrl_uart6: uart6grp {
+                       fsl,pins = <
+                               MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
+                               MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
+                               MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
+                               MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD1_CMD__SD1_CMD               0x59
+                               MX7D_PAD_SD1_CLK__SD1_CLK               0x19
+                               MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
+                               MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
+                               MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
+                               MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
+                               MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
+                               MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
+                               MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
+                       >;
+               };
+
+               pinctrl_usdhc2: usdhc2grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD               0x59
+                               MX7D_PAD_SD2_CLK__SD2_CLK               0x19
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
+                       >;
+               };
+
+               pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
+                               MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
+                       >;
+               };
+
+               pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
+                               MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
+                               MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
+                               MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
+                               MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
+                               MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
+                       >;
+               };
+
+
+               pinctrl_usdhc3: usdhc3grp {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD               0x59
+                               MX7D_PAD_SD3_CLK__SD3_CLK               0x19
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
+                               MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+                       fsl,pins = <
+                               MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
+                               MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
+                               MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
+                               MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
+                               MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
+                               MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
+                               MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
+                               MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
+                               MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
+                               MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
+                               MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
+                       >;
+               };
+       };
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>;
+       status = "okay";
+};
+
+&iomuxc_lpsr {
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
+               >;
+       };
+
+       pinctrl_pwm1: pwm1grp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x30
+               >;
+       };
+
+       pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
+               fsl,pins = <
+                       MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7       0x14
+               >;
+       };
+};
index f1120d6..70490ba 100644 (file)
@@ -16,7 +16,6 @@
 #include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <miiphy.h>
-#include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include "../common/pfuze.h"
@@ -29,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
        PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
        PAD_CTL_DSE_3P3V_49OHM)
 
@@ -170,30 +164,6 @@ static int setup_lcd(void)
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
-       MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-       MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-       MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
-};
-
-static void setup_iomux_fec(void)
-{
-       imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-}
-#endif
-
 static void setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -216,37 +186,6 @@ int mmc_map_to_kernel_blk(int dev_no)
 }
 
 #ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
-       int ret;
-       unsigned int gpio;
-
-       ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
-       if (ret) {
-               printf("GPIO: 'gpio_spi@0_5' not found\n");
-               return -ENODEV;
-       }
-
-       ret = gpio_request(gpio, "fec_rst");
-       if (ret && ret != -EBUSY) {
-               printf("gpio: requesting pin %u failed\n", gpio);
-               return ret;
-       }
-
-       gpio_direction_output(gpio, 0);
-       udelay(500);
-       gpio_direction_output(gpio, 1);
-
-       setup_iomux_fec();
-
-       ret = fecmxc_initialize_multi(bis, 0,
-               CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-       if (ret)
-               printf("FEC1 MXC: %s:failed\n", __func__);
-
-       return ret;
-}
-
 static int setup_fec(void)
 {
        struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
@@ -260,7 +199,6 @@ static int setup_fec(void)
        return set_clk_enet(ENET_125MHZ);
 }
 
-
 int board_phy_config(struct phy_device *phydev)
 {
        /* enable rgmii rxc skew and phy mode select to RGMII copper */
index 2a9fdac..a85db33 100644 (file)
@@ -59,6 +59,12 @@ CONFIG_MTD=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
index 865ce30..c105560 100644 (file)
@@ -61,6 +61,12 @@ CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
index 7455075..f574669 100644 (file)
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN          (32 * SZ_1M)
 
-/* Network */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_MXC_PHYADDR          0
-
-#define CONFIG_PHY_BROADCOM
-/* ENET1 */
-#define IMX_FEC_BASE                   ENET_IPS_BASE_ADDR
-
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0