clk: bcm2835: Don't cache the PLLB rate

The PLLB rate will be changed through the firmware clocks drivers and will
change behind this drivers' back, so we don't want to cache the rate.

Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/9864daba2f584ed49aee5ed1d2f4d48507c58197.1592210452.git-series.maxime@cerno.tech
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index b50f00f..027eba3 100644 (file)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1700,7 +1700,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 
                .min_rate = 600000000u,
                .max_rate = 3000000000u,
-               .max_fb_rate = BCM2835_MAX_FB_RATE),
+               .max_fb_rate = BCM2835_MAX_FB_RATE,
+               .flags = CLK_GET_RATE_NOCACHE),
        [BCM2835_PLLB_ARM]      = REGISTER_PLL_DIV(
                SOC_ALL,
                .name = "pllb_arm",
@@ -1710,7 +1711,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
                .load_mask = CM_PLLB_LOADARM,
                .hold_mask = CM_PLLB_HOLDARM,
                .fixed_divider = 1,
-               .flags = CLK_SET_RATE_PARENT),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
 
        /*
         * PLLC is the core PLL, used to drive the core VPU clock.