MIPS: Kernel: Identify Loongson-2K processors

Loongson-2K (Loongson64 Reduced) is a family of SoC shipped with
gs264e core.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 216a229..46c190e 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -250,6 +250,10 @@
 #define PRID_REV_LOONGSON1C            0x0020  /* Same as Loongson-1B */
 #define PRID_REV_LOONGSON2E            0x0002
 #define PRID_REV_LOONGSON2F            0x0003
+#define PRID_REV_LOONGSON2K_R1_0       0x0000
+#define PRID_REV_LOONGSON2K_R1_1       0x0001
+#define PRID_REV_LOONGSON2K_R1_2       0x0002
+#define PRID_REV_LOONGSON2K_R1_3       0x0003
 #define PRID_REV_LOONGSON3A_R1         0x0005
 #define PRID_REV_LOONGSON3B_R1         0x0006
 #define PRID_REV_LOONGSON3B_R2         0x0007

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f21a230..6de14b5 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1935,7 +1935,24 @@ platform:
 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 {
        switch (c->processor_id & PRID_IMP_MASK) {
-       case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */
+       case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
+               switch (c->processor_id & PRID_REV_MASK) {
+               case PRID_REV_LOONGSON2K_R1_0:
+               case PRID_REV_LOONGSON2K_R1_1:
+               case PRID_REV_LOONGSON2K_R1_2:
+               case PRID_REV_LOONGSON2K_R1_3:
+                       c->cputype = CPU_LOONGSON64;
+                       __cpu_name[cpu] = "Loongson-2K";
+                       set_elf_platform(cpu, "gs264e");
+                       set_isa(c, MIPS_CPU_ISA_M64R2);
+                       break;
+               }
+               decode_configs(c);
+               c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+               c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
+                               MIPS_ASE_LOONGSON_EXT2);
+               break;
+       case PRID_IMP_LOONGSON_64C:  /* Loongson-3 Classic */
                switch (c->processor_id & PRID_REV_MASK) {
                case PRID_REV_LOONGSON3A_R2_0:
                case PRID_REV_LOONGSON3A_R2_1:

diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 37f8e78..60d8c2a 100644 (file)
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -180,7 +180,8 @@ void __init check_wait(void)
                break;
        case CPU_LOONGSON64:
                if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
-                               (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0))
+                               (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
+                               (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
                        cpu_wait = r4k_wait;
                break;
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 89b6839..85eb62e 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1303,7 +1303,8 @@ static void probe_pcache(void)
                                          c->dcache.linesz;
                c->dcache.waybit = 0;
                if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
-                               (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0))
+                               (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
+                               (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
                        c->options |= MIPS_CPU_PREFETCH;
                break;
 
@@ -1629,8 +1630,13 @@ static void __init loongson3_sc_init(void)
        scache_size = c->scache.sets *
                                  c->scache.ways *
                                  c->scache.linesz;
-       /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
-       scache_size *= 4;
+
+       /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
+       if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
+               scache_size *= 2;
+       else
+               scache_size *= 4;
+
        c->scache.waybit = 0;
        c->scache.waysize = scache_size / c->scache.ways;
        pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",