drm/i915/fdi: move intel_update_fdi_pll_freq to intel_fdi.c
authorJani Nikula <jani.nikula@intel.com>
Wed, 25 Aug 2021 15:47:48 +0000 (18:47 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 27 Aug 2021 08:43:36 +0000 (11:43 +0300)
Move FDI related functions to intel_fdi.c. Rename to have intel_fdi
prefix while at it.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/da1609dfce4623f8ec86254aea6c2c8679b6a37f.1629906431.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_fdi.c
drivers/gpu/drm/i915/display/intel_fdi.h

index fe5ad59..a25cad6 100644 (file)
@@ -11546,22 +11546,6 @@ fail:
        drm_modeset_acquire_fini(&ctx);
 }
 
-static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv)
-{
-       if (IS_IRONLAKE(dev_priv)) {
-               u32 fdi_pll_clk =
-                       intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
-
-               dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
-       } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
-               dev_priv->fdi_pll_freq = 270000;
-       } else {
-               return;
-       }
-
-       drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq);
-}
-
 static int intel_initial_commit(struct drm_device *dev)
 {
        struct drm_atomic_state *state = NULL;
@@ -11815,7 +11799,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
 
        intel_plane_possible_crtcs_init(i915);
        intel_shared_dpll_init(dev);
-       intel_update_fdi_pll_freq(i915);
+       intel_fdi_pll_freq_update(i915);
 
        intel_update_czclk(i915);
        intel_modeset_init_hw(i915);
index 13f8ba4..88a78da 100644 (file)
@@ -95,6 +95,22 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
        }
 }
 
+void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
+{
+       if (IS_IRONLAKE(i915)) {
+               u32 fdi_pll_clk =
+                       intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
+
+               i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+       } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
+               i915->fdi_pll_freq = 270000;
+       } else {
+               return;
+       }
+
+       drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+}
+
 int intel_fdi_link_freq(struct drm_i915_private *i915,
                        const struct intel_crtc_state *pipe_config)
 {
index 2c8ffd9..cda9a32 100644 (file)
@@ -23,5 +23,6 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state);
 void intel_fdi_init_hook(struct drm_i915_private *dev_priv);
 void hsw_fdi_link_train(struct intel_encoder *encoder,
                        const struct intel_crtc_state *crtc_state);
+void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
 
 #endif