* mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):

	Add tx49 insns and configury.

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 7238cc1..18961bc 100644 (file)
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -249,6 +249,34 @@ else
        done
 fi
 
+tx49_files="ChangeLog mips-opc.c"
+if ( echo $* | grep keep\-tx49 > /dev/null ) ; then
+       for i in $tx49_files ; do
+               if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Keeping tx49 stuff in $i
+                       fi
+               fi
+       done
+else
+       for i in $tx49_files ; do
+               if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Removing traces of \"tx49\" from $i...
+                       fi
+                       cp $i new
+                       sed '/start\-sanitize\-tx49/,/end-\sanitize\-tx49/d' < $i > new
+                       if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+                               if [ -n "${verbose}" ] ; then
+                                       echo Caching $i in .Recover...
+                               fi
+                               mv $i .Recover
+                       fi
+                       mv new $i
+               fi
+       done
+fi
+
 tic80_files="ChangeLog Makefile.in Makefile.am configure.in configure disassemble.c"
 if ( echo $* | grep keep\-tic80 > /dev/null ) ; then
        for i in $tic80_files ; do

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 665d1d1..b02ce4e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+start-sanitize-tx49
+Wed Oct 29 15:10:56 1997  Gavin Koch  <gavin@cygnus.com>
+
+       * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): 
+       Add tx49 insns and configury.
+
+end-sanitize-tx49
 Tue Oct 28 17:59:32 1997  Ken Raeburn  <raeburn@cygnus.com>
 
        * mips-opc.c (ffc, ffs): Fix mask.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 03305a8..5ca5ef2 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -76,6 +76,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define L1     INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
+/* start-sanitize-tx49 */
+#define T4      INSN_4900
+/* end-sanitize-tx49 */
 /* start-sanitize-vr5400 */
 #define N5     INSN_5400
 /* end-sanitize-vr5400 */
@@ -84,11 +87,20 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 /* end-sanitize-r5900 */
 
 #define G1      (T3                   \
+/* start-sanitize-tx49 */             \
+                 | T4                 \
+/* end-sanitize-tx49 */               \
 /* start-sanitize-r5900 */            \
                  | T5                 \
 /* end-sanitize-r5900 */              \
                  )
 
+#define G2      (T3                   \
+/* start-sanitize-tx49 */             \
+                 | T4                 \
+/* end-sanitize-tx49 */               \
+                 )
+
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -312,7 +324,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,   I3      },
-{"deret",   "",         0x4200001f, 0xffffffff,    0,  T3      },
+{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2      },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 {"ddiv",    "d,v,t",   3,    (int) M_DDIV_3,   INSN_MACRO      },
@@ -357,8 +369,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"dmulo",   "d,v,I",   3,    (int) M_DMULO_I,  INSN_MACRO      },
 {"dmulou",  "d,v,t",   3,    (int) M_DMULOU,   INSN_MACRO      },
 {"dmulou",  "d,v,I",   3,    (int) M_DMULOU_I, INSN_MACRO      },
-{"dmult",   "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
-{"dmultu",  "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
+{"dmult",   "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      I3},
+{"dmult",   "d,s,t",   0x0000001c, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
+{"dmultu",  "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,      I3},
+{"dmultu",  "d,s,t",   0x0000001d, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d, T4},
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,      I3      }, /* dsubu 0*/
 {"drem",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
@@ -505,20 +519,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       T5      },
   /* end-sanitize-r5900 */
 {"madd",    "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T3      },
-{"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T3      },
+{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          G1      },
+{"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     G1      },
   /* start-sanitize-r5900 */
-{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
-{"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 {"madd1",   "s,t",     0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 {"madd1",   "d,s,t",   0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
   /* end-sanitize-r5900 */
 {"maddu",   "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T3      },
-{"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T3      },
+{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          G1      },
+{"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     G1      },
   /* start-sanitize-r5900 */
-{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
-{"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
 {"maddu1",  "s,t",     0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          T5      },
 {"maddu1",  "d,s,t",   0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d,     T5      },
   /* end-sanitize-r5900 */
@@ -772,7 +782,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"pxor",   "d,v,t",    0x700004c9, 0xfc0007ff, WR_d|RD_s|RD_t, T5      },
   /* end-sanitize-r5900 */
 
-{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,   I4      },
+{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,   I4|T4   },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 
   /* start-sanitize-r5900 */
@@ -816,8 +826,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"sd",     "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,   I3      },
 {"sd",      "t,o(b)",  0,    (int) M_SD_OB,    INSN_MACRO      },
 {"sd",      "t,A(b)",  0,    (int) M_SD_AB,    INSN_MACRO      },
-{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           T3      },
-{"sdbbp",   "c",       0x0000000e, 0xfc00003f, TRAP,           T3      },
+{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           G2      },
+{"sdbbp",   "c",       0x0000000e, 0xfc00003f, TRAP,           G2      },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "T,A(b)",  2,    (int) M_SDC1_AB,  INSN_MACRO      },