gallium: add PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
authorMarek Olšák <marek.olsak@amd.com>
Wed, 23 May 2018 21:45:50 +0000 (17:45 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Tue, 31 Jul 2018 22:28:41 +0000 (18:28 -0400)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
18 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/v3d/v3d_screen.c
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h

index d7ce521..5fc49e2 100644 (file)
@@ -411,6 +411,17 @@ The integer capabilities:
 * ``PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES``: Limit on combined shader
   output resources (images + buffers + fragment outputs). If 0 the state
   tracker works it out.
+* ``PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS``: This determines limitations
+  on the number of samples that framebuffer attachments can have.
+  Possible values:
+    0: color.nr_samples == zs.nr_samples == color.nr_storage_samples
+       (standard MSAA quality)
+    1: color.nr_samples >= zs.nr_samples == color.nr_storage_samples
+       (enhanced MSAA quality)
+    2: color.nr_samples >= zs.nr_samples >= color.nr_storage_samples
+       (full flexibility in tuning MSAA quality and performance)
+  All color attachments must have the same number of samples and the same
+  number of storage samples.
 * ``PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET``:
   Whether pipe_vertex_buffer::buffer_offset is treated as signed. The u_vbuf
   module needs this for optimal performance in workstation applications.
index 04c7a87..d4abf99 100644 (file)
@@ -270,6 +270,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 5aefc3d..4d54446 100644 (file)
@@ -354,6 +354,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
        case PIPE_CAP_TILE_RASTER_ORDER:
        case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
        case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
        case PIPE_CAP_FENCE_SIGNAL:
        case PIPE_CAP_CONSTBUF0_FLAGS:
index a03840a..132a9fc 100644 (file)
@@ -328,6 +328,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 9921a94..0d0a345 100644 (file)
@@ -359,6 +359,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 155ddee..bddb2e6 100644 (file)
@@ -225,6 +225,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 44a1a8a..9f8bb46 100644 (file)
@@ -275,6 +275,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index bcd30b5..a206db3 100644 (file)
@@ -304,6 +304,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 3331a6e..0616809 100644 (file)
@@ -247,6 +247,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
         case PIPE_CAP_TILE_RASTER_ORDER:
         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+        case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
         case PIPE_CAP_FENCE_SIGNAL:
index 2518032..ffed69a 100644 (file)
@@ -422,6 +422,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_FENCE_SIGNAL:
        case PIPE_CAP_CONSTBUF0_FLAGS:
        case PIPE_CAP_PACKED_UNIFORMS:
+       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
        case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
        case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
        case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
index b8ee873..6e80479 100644 (file)
@@ -312,6 +312,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
        case PIPE_CAP_MAX_RENDER_TARGETS:
                return 8;
+       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
+               return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
 
        case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
        case PIPE_CAP_MIN_TEXEL_OFFSET:
index ed8f8d9..207ecc7 100644 (file)
@@ -311,6 +311,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 9d9b797..b8f936e 100644 (file)
@@ -463,6 +463,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 65fa1bc..19d6f44 100644 (file)
@@ -344,6 +344,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index e08239f..b274f2d 100644 (file)
@@ -261,6 +261,7 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_TILE_RASTER_ORDER:
         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
         case PIPE_CAP_CONSTBUF0_FLAGS:
         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
index 17776fa..1bd60d1 100644 (file)
@@ -287,6 +287,7 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_LOAD_CONSTBUF:
         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
         case PIPE_CAP_FENCE_SIGNAL:
index 01e8eae..cfa0e8b 100644 (file)
@@ -286,6 +286,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
    case PIPE_CAP_TILE_RASTER_ORDER:
    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
    case PIPE_CAP_FENCE_SIGNAL:
index 02e0c80..9909b2b 100644 (file)
@@ -802,6 +802,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
    PIPE_CAP_TILE_RASTER_ORDER,
    PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES,
+   PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS,
    PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
    PIPE_CAP_CONTEXT_PRIORITY_MASK,
    PIPE_CAP_FENCE_SIGNAL,