void icache_enable(void)
{
+#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
);
#endif
#endif
+#endif
}
void dcache_enable(void)
{
+#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_RISCV_MMODE
#ifdef CONFIG_TARGET_LIGHT_C910
asm volatile (
);
#endif
#endif
+#endif
}
.align 2
.global trap_entry
trap_entry:
+#ifndef CONFIG_THEAD_PLIC
ebreak
+#endif
addi sp, sp, -32 * REGBYTES
SREG x1, 1 * REGBYTES(sp)
SREG x2, 2 * REGBYTES(sp)
dtb-$(CONFIG_TARGET_ICE_C910) += ice-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_EVB_MPW_C910) += light-evb-mpw-c910.dtb
dtb-$(CONFIG_TARGET_LIGHT_FPGA_FM_C910) += light-fpga-fm-c910.dtb
-dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-evt.dtb
+dtb-$(CONFIG_TARGET_LIGHT_C910) += light-a-ref.dtb light-b-ref.dtb light-a-val.dtb light-b-product.dtb light-a-product.dtb light-ant-ref.dtb light-beagle.dtb light-b-power.dtb
targets += $(dtb-y)
--- /dev/null
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "okay";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
+ lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
ranges;
u-boot,dm-pre-reloc;
+ intc: interrupt-controller@ffd8000000 {
+ compatible = "riscv,plic0";
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ status = "disabled";
+ };
+
dummy_apb: apb-clock {
compatible = "fixed-clock";
clock-frequency = <62500000>;
+++ /dev/null
-/dts-v1/;
-/ {
- model = "T-HEAD c910 light";
- compatible = "thead,c910_light";
- #address-cells = <2>;
- #size-cells = <2>;
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0xc0000000 0x0 0x40000000>;
- };
-
- aliases {
- spi0 = &spi0;
- spi1 = &qspi0;
- spi2 = &qspi1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <3000000>;
- u-boot,dm-pre-reloc;
- cpu@0 {
- device_type = "cpu";
- reg = <0>;
- status = "okay";
- compatible = "riscv";
- riscv,isa = "rv64imafdcvsu";
- mmu-type = "riscv,sv39";
- u-boot,dm-pre-reloc;
- };
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- ranges;
- u-boot,dm-pre-reloc;
-
- dummy_apb: apb-clock {
- compatible = "fixed-clock";
- clock-frequency = <62500000>;
- clock-output-names = "dummy_apb";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_ahb: ahb-clock {
- compatible = "fixed-clock";
- clock-frequency = <250000000>;
- clock-output-names = "core";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_spi: spi-clock {
- compatible = "fixed-clock";
- clock-frequency = <396000000>;
- clock-output-names = "dummy_spi";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_qspi0: qspi0-clock {
- compatible = "fixed-clock";
- clock-frequency = <792000000>;
- clock-output-names = "dummy_qspi0";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_uart_sclk: uart-sclk-clock {
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "dummy_uart_sclk";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_i2c_icclk: i2c-icclk-clock {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "dummy_i2c_icclk";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_dpu_pixclk: dpu-pix-clock {
- compatible = "fixed-clock";
- clock-frequency = <74250000>;
- clock-output-names = "dummy_dpu_pixclk";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- dummy_dphy_refclk: dphy-ref-clock {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "dummy_dpu_refclk";
- #clock-cells = <0>;
- u-boot,dm-pre-reloc;
- };
-
- i2c0: i2c@ffe7f20000 {
- compatible = "snps,designware-i2c";
- reg = <0xff 0xe7f20000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@ffe7f24000{
- compatible = "snps,designware-i2c";
- reg = <0xff 0xe7f24000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@ffec00c000{
- compatible = "snps,designware-i2c";
- reg = <0xff 0xec00c000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c3: i2c@ffec014000{
- compatible = "snps,designware-i2c";
- reg = <0xff 0xec014000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c4: i2c@ffe7f28000{
- compatible = "snps,designware-i2c";
- reg = <0xff 0xe7f28000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcal6408ahk_a: gpio@20 {
- compatible = "nxp,pca9554";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
- i2c5: i2c@fff7f2c000{
- compatible = "snps,designware-i2c";
- reg = <0xff 0xf7f2c000 0x0 0x4000>;
- clocks = <&dummy_i2c_icclk>;
- clock-frequency = <100000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- serial@ffe7014000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xff 0xe7014000 0x0 0x400>;
- clocks = <&dummy_uart_sclk>;
- clock-frequency = <100000000>;
- clock-names = "baudclk";
- reg-shift = <2>;
- reg-io-width = <4>;
- u-boot,dm-pre-reloc;
- };
-
- gmac0: ethernet@ffe7070000 {
- compatible = "snps,dwmac";
- reg = <0xff 0xe7070000 0x0 0x2000>;
- clocks = <&dummy_apb>;
- clock-names = "stmmaceth";
- snps,pbl = <32>;
- snps,fixed-burst;
-
- phy-mode = "rgmii-id";
- phy-handle = <&phy_88E1111_a>;
- status = "okay";
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy_88E1111_a: ethernet-phy@1 {
- reg = <0x1>;
- };
-
- phy_88E1111_b: ethernet-phy@2 {
- reg = <0x2>;
- };
- };
- };
-
- gmac1: ethernet@ffe7060000 {
- compatible = "snps,dwmac";
- reg = <0xff 0xe7060000 0x0 0x2000>;
- clocks = <&dummy_apb>;
- clock-names = "stmmaceth";
- snps,pbl = <32>;
- snps,fixed-burst;
- phy-mode = "rgmii-id";
- phy-handle = <&phy_88E1111_b>;
- status = "disabled";
- };
-
- emmc: sdhci@ffe7080000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0xff 0xe7080000 0x0 0x10000>;
- index = <0x0>;
- clocks = <&dummy_ahb>;
- clock-frequency = <198000000>;
- clock-names = "core";
- max-frequency = <198000000>;
- sdhci-caps-mask = <0x0 0x1000000>;
- mmc-hs400-1_8v;
- non-removable;
- no-sdio;
- no-sd;
- bus-width = <8>;
- voltage= "1.8v";
- pull_up;
- io_fixed_1v8;
- fifo-mode;
- u-boot,dm-pre-reloc;
- };
-
- sdhci0: sd@ffe7090000 {
- compatible = "snps,dwcmshc-sdhci";
- reg = <0xff 0xe7090000 0x0 0x10000>;
- index = <0x1>;
- clocks = <&dummy_ahb>;
- clock-frequency = <198000000>;
- max-frequency = <198000000>;
- sd-uhs-sdr104;
- pull_up;
- clock-names = "core";
- bus-width = <4>;
- voltage= "3.3v";
- };
-
- qspi0: spi@ffea000000 {
- compatible = "snps,dw-apb-ssi-quad";
- reg = <0xff 0xea000000 0x0 0x1000>;
- clocks = <&dummy_qspi0>;
- num-cs = <1>;
- cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
- spi-max-frequency = <100000000>;
- #address-cells = <1>;
- #size-cells =<0>;
- status = "disabled";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- reg = <0>;
- };
- };
-
- qspi1: spi@fff8000000 {
- compatible = "snps,dw-apb-ssi-quad";
- reg = <0xff 0xf8000000 0x0 0x1000>;
- clocks = <&dummy_spi>;
- num-cs = <1>;
- cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
- spi-max-frequency = <66000000>;
- #address-cells = <1>;
- #size-cells =<0>;
- status = "disabled";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- reg = <0>;
- };
- };
-
- spi0: spi@ffe700c000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0xff 0xe700c000 0x0 0x1000>;
- clocks = <&dummy_spi>;
- cs-gpio = <&gpio2_porta 15 0>;
- spi-max-frequency = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- };
- };
-
- gpio2: gpio@ffe7f34000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xe7f34000 0x0 0x1000>;
- clocks = <&dummy_apb>;
- #address-cells = <1>;
- #size-cells = <0>;
- gpio2_porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <32>;
- reg = <0>;
- };
- };
-
- gpio0: gpio@ffec005000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xec005000 0x0 0x1000>;
- clocks = <&dummy_apb>;
- #address-cells = <1>;
- #size-cells = <0>;
- gpio0_porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <32>;
- reg = <0>;
- };
- };
-
- gpio1: gpio@ffec006000 {
- compatible = "snps,dw-apb-gpio";
- reg = <0xff 0xec006000 0x0 0x1000>;
- clocks = <&dummy_apb>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio1_porta: gpio-controller@0 {
- compatible = "snps,dw-apb-gpio-port";
- gpio-controller;
- #gpio-cells = <2>;
- snps,nr-gpios = <32>;
- reg = <0>;
- };
- };
-
- pwm: pwm@ffec01c000 {
- compatible = "thead,pwm-light";
- reg = <0xff 0xec01c000 0x0 0x4000>;
- #pwm-cells = <2>;
- };
-
- dsi_regs: dsi-controller@ffef500000 {
- compatible = "thead,light-dsi-regs", "syscon";
- reg = <0xff 0xef500000 0x0 0x10000>;
- status = "okay";
- };
-
- vosys_regs: vosys@ffef528000 {
- compatible = "thead,light-vo-subsys", "syscon";
- reg = <0xff 0xef528000 0x0 0x1000>;
- status = "okay";
- };
-
- dpu: dc8200@ffef600000 {
- compatible = "verisilicon,dc8200";
- reg = <0xff 0xef600000 0x0 0x100>;
- };
-
- axiscr {
- compatible = "thead,axiscr";
- reg = <0xff 0xff004000 0x0 0x1000>;
- lock-read = "okay";
- lock-write = "okay";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- axiscr0: axisrc@0 {
- device_type = "axiscr";
- region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- };
- axiscr1: axisrc@1 {
- device_type = "axiscr";
- region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- };
- axiscr2: axisrc@2 {
- device_type = "axiscr";
- region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- };
- };
-
- axiparity {
- compatible = "thead,axiparity";
- reg = <0xff 0xff00c000 0x0 0x1000>;
- lock = "okay";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- axiparity0: axiparity@0 {
- device_type = "axiparity";
- region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- };
- axiparity1: axiparity@1 {
- device_type = "axiparity";
- region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
- };
- };
-
- dsi_bridge: dsi-bridge {
- compatible = "thead,light-dsi-bridge";
- clocks = <&dummy_dpu_pixclk>;
- clock-names = "pix-clk";
- phys = <&dsi_dphy>;
- phy-names = "dphy";
- };
-
- dsi_host: dsi-host {
- compatible = "synopsys,dw-mipi-dsi";
- regmap = <&dsi_regs>;
- status = "okay";
- };
-
- dsi_dphy: dsi-dphy {
- compatible = "synopsys,dw-dphy";
- regmap = <&dsi_regs>;
- vosys-regmap = <&vosys_regs>;
- clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
- clock-names = "pix-clk", "ref-clk";
- #phy-cells = <0>;
- status = "okay";
- };
-
- lcd_backlight: pwm-backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm 0 5000000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
- };
-
- ili9881c_panel {
- compatible = "ilitek,ili9881c";
- backlight = <&lcd_backlight>;
- reset-gpios = <&gpio1_porta 5 1>; /* active low */
- lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
- lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
- };
- };
-
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = "/soc/serial@ffe7014000:115200";
- };
-};
--- /dev/null
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "disabled";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
+ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
--- /dev/null
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "disabled";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
+ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
#address-cells = <1>;
#size-cells = <0>;
-
- pcal6408ahk_a: gpio@20 {
- compatible = "nxp,pca9554";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
i2c5: i2c@fff7f2c000{
--- /dev/null
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "disabled";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ status = "disabled";
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&gpio1_porta 9 0>; /* active high */
+ lcd-bias-en-gpios = <&gpio1_porta 10 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
--- /dev/null
+/dts-v1/;
+/ {
+ model = "T-HEAD c910 light";
+ compatible = "thead,c910_light";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0xc0000000 0x0 0x40000000>;
+ };
+
+ aliases {
+ spi0 = &spi0;
+ spi1 = &qspi0;
+ spi2 = &qspi1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+ u-boot,dm-pre-reloc;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcvsu";
+ mmu-type = "riscv,sv39";
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+ u-boot,dm-pre-reloc;
+
+ intc: interrupt-controller@ffd8000000 {
+ compatible = "riscv,plic0";
+ reg = <0xff 0xd8000000 0x0 0x04000000>;
+ status = "disabled";
+ };
+
+ dummy_apb: apb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <62500000>;
+ clock-output-names = "dummy_apb";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_ahb: ahb-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ clock-output-names = "core";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_spi: spi-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <396000000>;
+ clock-output-names = "dummy_spi";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_qspi0: qspi0-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <792000000>;
+ clock-output-names = "dummy_qspi0";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "dummy_uart_sclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_i2c_icclk: i2c-icclk-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "dummy_i2c_icclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dpu_pixclk: dpu-pix-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <74250000>;
+ clock-output-names = "dummy_dpu_pixclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ dummy_dphy_refclk: dphy-ref-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "dummy_dpu_refclk";
+ #clock-cells = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ i2c0: i2c@ffe7f20000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f20000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ffe7f24000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f24000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@ffec00c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec00c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@ffec014000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xec014000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@ffe7f28000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xe7f28000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcal6408ahk_a: gpio@20 {
+ compatible = "nxp,pca9554";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c5: i2c@fff7f2c000{
+ compatible = "snps,designware-i2c";
+ reg = <0xff 0xf7f2c000 0x0 0x4000>;
+ clocks = <&dummy_i2c_icclk>;
+ clock-frequency = <100000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x400>;
+ clocks = <&dummy_uart_sclk>;
+ clock-frequency = <100000000>;
+ clock-names = "baudclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
+ };
+
+ gmac0: ethernet@ffe7070000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7070000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_a>;
+ status = "okay";
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy_88E1111_a: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ phy_88E1111_b: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+ };
+
+ gmac1: ethernet@ffe7060000 {
+ compatible = "snps,dwmac";
+ reg = <0xff 0xe7060000 0x0 0x2000>;
+ clocks = <&dummy_apb>;
+ clock-names = "stmmaceth";
+ snps,pbl = <32>;
+ snps,fixed-burst;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy_88E1111_b>;
+ status = "okay";
+ };
+
+ emmc: sdhci@ffe7080000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ index = <0x0>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ clock-names = "core";
+ max-frequency = <198000000>;
+ sdhci-caps-mask = <0x0 0x1000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ bus-width = <8>;
+ voltage= "1.8v";
+ pull_up;
+ io_fixed_1v8;
+ fifo-mode;
+ u-boot,dm-pre-reloc;
+ };
+
+ sdhci0: sd@ffe7090000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ index = <0x1>;
+ clocks = <&dummy_ahb>;
+ clock-frequency = <198000000>;
+ max-frequency = <198000000>;
+ sd-uhs-sdr104;
+ pull_up;
+ clock-names = "core";
+ bus-width = <4>;
+ voltage= "3.3v";
+ };
+
+ qspi0: spi@ffea000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xea000000 0x0 0x1000>;
+ clocks = <&dummy_qspi0>;
+ num-cs = <1>;
+ cs-gpio = <&gpio2_porta 3 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ qspi1: spi@fff8000000 {
+ compatible = "snps,dw-apb-ssi-quad";
+ reg = <0xff 0xf8000000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ num-cs = <1>;
+ cs-gpio = <&gpio0_porta 1 0>; // GPIO_ACTIVE_HIGH: 0
+ spi-max-frequency = <66000000>;
+ #address-cells = <1>;
+ #size-cells =<0>;
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+ };
+ };
+
+ spi0: spi@ffe700c000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ clocks = <&dummy_spi>;
+ cs-gpio = <&gpio2_porta 15 0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio2_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio0_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ clocks = <&dummy_apb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1_porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <32>;
+ reg = <0>;
+ };
+ };
+
+ pwm: pwm@ffec01c000 {
+ compatible = "thead,pwm-light";
+ reg = <0xff 0xec01c000 0x0 0x4000>;
+ #pwm-cells = <2>;
+ };
+
+ dsi_regs: dsi-controller@ffef500000 {
+ compatible = "thead,light-dsi-regs", "syscon";
+ reg = <0xff 0xef500000 0x0 0x10000>;
+ status = "okay";
+ };
+
+ vosys_regs: vosys@ffef528000 {
+ compatible = "thead,light-vo-subsys", "syscon";
+ reg = <0xff 0xef528000 0x0 0x1000>;
+ status = "okay";
+ };
+
+ dpu: dc8200@ffef600000 {
+ compatible = "verisilicon,dc8200";
+ reg = <0xff 0xef600000 0x0 0x100>;
+ };
+
+ axiscr {
+ compatible = "thead,axiscr";
+ reg = <0xff 0xff004000 0x0 0x1000>;
+ lock-read = "okay";
+ lock-write = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiscr0: axisrc@0 {
+ device_type = "axiscr";
+ region = <0x00 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr1: axisrc@1 {
+ device_type = "axiscr";
+ region = <0x00 0x80000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiscr2: axisrc@2 {
+ device_type = "axiscr";
+ region = <0x01 0x00000000 0x00 0x80000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ axiparity {
+ compatible = "thead,axiparity";
+ reg = <0xff 0xff00c000 0x0 0x1000>;
+ lock = "okay";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ axiparity0: axiparity@0 {
+ device_type = "axiparity";
+ region = <0x00 0x00000000 0x01 0x0000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ axiparity1: axiparity@1 {
+ device_type = "axiparity";
+ region = <0x01 0x00000000 0x01 0x00000000>; // 4KB align
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ dsi_bridge: dsi-bridge {
+ compatible = "thead,light-dsi-bridge";
+ clocks = <&dummy_dpu_pixclk>;
+ clock-names = "pix-clk";
+ phys = <&dsi_dphy>;
+ phy-names = "dphy";
+ };
+
+ dsi_host: dsi-host {
+ compatible = "synopsys,dw-mipi-dsi";
+ regmap = <&dsi_regs>;
+ status = "okay";
+ };
+
+ dsi_dphy: dsi-dphy {
+ compatible = "synopsys,dw-dphy";
+ regmap = <&dsi_regs>;
+ vosys-regmap = <&vosys_regs>;
+ clocks = <&dummy_dpu_pixclk>, <&dummy_dphy_refclk>;
+ clock-names = "pix-clk", "ref-clk";
+ #phy-cells = <0>;
+ status = "okay";
+ };
+
+ lcd_backlight: pwm-backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ ili9881c_panel {
+ compatible = "ilitek,ili9881c";
+ backlight = <&lcd_backlight>;
+ reset-gpios = <&gpio1_porta 5 1>; /* active low */
+ lcd-en-gpios = <&pcal6408ahk_a 2 0>; /* active high */
+ lcd-bias-en-gpios = <&pcal6408ahk_a 4 0>;/* active high */
+ };
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "/soc/serial@ffe7014000:115200";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#ifndef _LIGHT_PLIC_H
+#define _LIGHT_PLIC_H
+
+/*
+ * M-mode
+ * hart id: 0, 2, 4, 6
+ * S-mode
+ * hart id: 1, 3, 5, 7
+ */
+
+/* interrupt priority register */
+#define PLIC_PRIO_REG(base, id) ((void __iomem *)(base) + 0x00 + (id) * 4)
+
+/* enable register */
+#define PLIC_ENABLE_REG(base, hart) ((void __iomem *)(base) + 0x2000 + (hart) * 0x80)
+
+/* pending registr */
+#define PLIC_PENDING_REG(base, hart) ((void __iomem *)(base) + 0x1000 + ((hart) / 4) * 4)
+
+/* threshold register */
+#define PLIC_THRESHOLD_REG(base, hart) ((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x00)
+
+/* claim/complete register */
+#define PLIC_CLAIM_REG(base, hart) ((void __iomem *)(base) + 0x200000 + (hart) * 0x1000 + 0x04)
+
+#define MAX_IRQ_NUM 256
+typedef void (*irq_handler_t)(void);
+
+
+int irq_handler_register(int irq, irq_handler_t handler);
+
+void arch_local_irq_enable(void);
+
+void arch_local_irq_disable(void);
+
+void irq_enable(int hwirq);
+
+void irq_disable(int hwirq);
+
+void irq_priority_set(int prio);
+
+int plic_init(void);
+
+#endif
#include <linux/const.h>
/* Status register flags */
+#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
#define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
+#define MIE_MEIE (_AC(0x1, UL) << IRQ_M_EXT)
#define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
#define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
#define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
- *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
return (void *)*handle;
}
#ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint; /* clint base address */
#endif
-#ifdef CONFIG_ANDES_PLIC
+#if (defined CONFIG_ANDES_PLIC) || (defined CONFIG_THEAD_PLIC)
void __iomem *plic; /* plic base address */
#endif
#ifdef CONFIG_ANDES_PLMT
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
obj-$(CONFIG_THEAD_IPI) += thead_ipi.o
+obj-$(CONFIG_THEAD_PLIC) += thead_plic.o
else
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
#include <asm/system.h>
#include <asm/encoding.h>
+__attribute__((weak)) int plic_init(void)
+{
+ return 0;
+}
+
static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
{
static const char * const exception_code[] = {
int interrupt_init(void)
{
+ debug("[%s,%d]Initialize the plic\n", __func__, __LINE__);
+ plic_init();
return 0;
}
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
+ debug("[%s,%d]\n", __func__, __LINE__);
if (is_irq) {
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
+ debug("[%s,%d]\n", __func__, __LINE__);
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
_exit_trap(cause, epc, regs);
}
+ debug("[%s,%d]\n", __func__, __LINE__);
return epc;
}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Liuw <lw312886@alibaba-inc.com>
+ *
+ * U-Boot syscon driver for Thead's Platform Level Interrupt Controller (PLIC)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/csr.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+#include <asm/global_data.h>
+#include <cpu.h>
+#include <linux/err.h>
+#include <asm/arch-thead/light-plic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLIC_BASE_GET(void) \
+ do { \
+ long *ret; \
+ \
+ if (!gd->arch.plic) { \
+ ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+ gd->arch.plic = ret; \
+ } \
+ } while (0)
+
+irq_handler_t irq_table[MAX_IRQ_NUM];
+
+void __iomem *plic_base = NULL;
+
+void external_interrupt(struct pt_regs *regs)
+{
+ void __iomem *claim;
+ irq_handler_t handler;
+ u32 irq_num;
+
+ debug("[%s,%d]\n", __func__, __LINE__);
+ if (!plic_base)
+ return;
+
+ debug("[%s,%d]\n", __func__, __LINE__);
+ claim = PLIC_CLAIM_REG(plic_base, 0);
+
+ while ((irq_num = readl(claim))) {
+ if (irq_num >= MAX_IRQ_NUM)
+ debug("Cannot find irq:%d\n", irq_num);
+ else {
+ handler = irq_table[irq_num];
+ if (handler)
+ handler();
+ writel(irq_num, claim);
+ }
+ }
+ debug("[%s,%d]\n", __func__, __LINE__);
+}
+
+static void plic_toggle(void __iomem *enable_base, int hwirq, int enable)
+{
+ u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
+ u32 hwirq_mask = 1 << (hwirq % 32);
+
+ if (enable)
+ writel(readl(reg) | hwirq_mask, reg);
+ else
+ writel(readl(reg) & ~hwirq_mask, reg);
+
+ debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+ (unsigned long)reg, readl(reg));
+}
+
+static void plic_set_threshold(void __iomem *thre_base, u32 threshold)
+{
+ writel(threshold, thre_base);
+ debug("[%s,%d][0x%lx] = 0x%x\n", __func__, __LINE__,
+ (unsigned long)thre_base, readl(thre_base));
+}
+
+static void plic_set_irq_priority(void __iomem *prio_base, int prio)
+{
+ writel(prio, prio_base);
+}
+
+int irq_handler_register(int irq, irq_handler_t handler)
+{
+ if (irq < 0 || irq >= MAX_IRQ_NUM) {
+ debug("invalid irq number to register\n");
+ return -EINVAL;
+ }
+
+ irq_table[irq] = handler;
+
+ return 0;
+}
+
+void arch_local_irq_enable(void)
+{
+ csr_set(CSR_MIE, MIE_MEIE);
+ csr_set(CSR_MSTATUS, SR_MIE);
+}
+
+void arch_local_irq_disable(void)
+{
+ csr_clear(CSR_MIE, MIE_MEIE);
+ csr_clear(CSR_MSTATUS, SR_MIE);
+}
+
+void irq_priority_set(int irq_id)
+{
+ plic_set_irq_priority(PLIC_PRIO_REG(gd->arch.plic, irq_id), 4);
+}
+
+void irq_enable(int hwirq)
+{
+ plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 1);
+}
+
+void irq_disable(int hwirq)
+{
+ plic_toggle(PLIC_ENABLE_REG(gd->arch.plic, 0), hwirq, 0);
+}
+
+int plic_init()
+{
+ PLIC_BASE_GET();
+ if (IS_ERR(gd->arch.plic))
+ return PTR_ERR(gd->arch.plic);
+
+ plic_base = gd->arch.plic;
+ debug("THEAD PLIC BASE: 0x%lx\n", (unsigned long)gd->arch.plic);
+
+ plic_set_threshold(PLIC_THRESHOLD_REG(gd->arch.plic, 0), 0);
+
+ arch_local_irq_enable(); //enale the global interrupt
+
+ return 0;
+}
+
+static const struct udevice_id thead_plic_ids[] = {
+ { .compatible = "riscv,plic0", .data = RISCV_SYSCON_PLIC},
+ { }
+};
+
+U_BOOT_DRIVER(thead_plic) = {
+ .name = "thead_light_plic",
+ .id = UCLASS_SYSCON,
+ .of_match = thead_plic_ids,
+};
config DDR_REGU_0V6
int "uint in uv"
- default 640000
+ default 600000
config DDR_REGU_0V8
int "uint in uv"
- default 820000
+ default 800000
config DDR_REGU_1V1
int "uint in uv"
- default 1200000
+ default 1100000
config SYS_CPU
default "c9xx"
config LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B
bool "light board-b security boot with verification"
-config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
- bool "light ant evt security boot with verification"
+config LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
+ bool "light ant ref security boot with verification"
config TARGET_LIGHT_FPGA_FM_C910
bool "light fullmask FPGA board"
bool "light fullmask VAL board-a for system validation"
default n
+config TARGET_LIGHT_FM_C910_A_REF
+ bool "light fullmask reference A board"
+ default n
+
config TARGET_LIGHT_FM_C910_VAL_B
bool "light fullmask VAL board-b for system validation"
default n
-config TARGET_LIGHT_FM_C910_VAL_ANT_EVT
- bool "light fullmask for ant-evt board "
+config TARGET_LIGHT_FM_C910_B_REF
+ bool "light fullmask reference B board"
+ default n
+
+config TARGET_LIGHT_FM_C910_VAL_ANT_REF
+ bool "light fullmask for ant-ref board "
default n
config TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE
- bool "light fullmask for ant-evt board "
+ bool "light fullmask for ant-discrete board "
+ default n
+
+config TARGET_LIGHT_FM_C910_BEAGLE
+ bool "light fullmask for beagle board "
+ default n
+
+config TARGET_LIGHT_FM_C910_B_POWER
+ bool "light fullmask for light-b-power board "
default n
config SYS_TEXT_BASE
config SPL_TEXT_BASE
hex
- default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT
- default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+ default 0xffe0000800 if LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF
+ default 0xffe0000000 if !(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A || LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B || LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
config SPL_MAX_SIZE
hex
default 0x2f000
+config THEAD_PLIC
+ bool "Light PLIC Setting"
+ depends on RISCV_MMODE || SPL_RISCV_MMODE
+ select REGMAP
+ select SYSCON
+ default n
+ help
+ The Thead PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
+
+config THEAD_LIGHT_TIMER
+ bool "Light TIMER0 driver and test"
+ depends on THEAD_PLIC
+ default n
+ help
+ The timer driver to verify the plic interrupt framework is ready
+
+config THEAD_LIGHT_DIGITAL_SENSOR
+ bool "Light Digital Sensor Setting"
+ depends on THEAD_PLIC
+ default n
+ help
+ The security digital sensor driver
+
config BOARD_SPECIFIC_OPTIONS
def_bool y
select RISCV_THEAD
else # // CONFIG_SPL_BUILD
obj-y += light.o
obj-y += board.o
+obj-$(CONFIG_THEAD_LIGHT_TIMER) += timer.o
+obj-$(CONFIG_THEAD_LIGHT_DIGITAL_SENSOR) += digital_sensor.o digital_sensor_test.o
obj-y += clock_config.o
obj-y += sec_check.o
obj-y += boot.o
obj-y += light-sv/pll_io_test.o
obj-y += light-sv/adc_test.o
+obj-y += version_rollback.o
endif
#endif
static unsigned int upgrade_image_version = 0;
+int csi_rpmb_write_access_key(void)
+{
+ unsigned long *temp_rpmb_key_addr = NULL;
+ char runcmd[64] = {0};
+ uint8_t blkdata[256] = {0};
+ uint8_t kdf_rpmb_key[32];
+ uint32_t kdf_rpmb_key_length = 0;
+ int ret = 0;
+
+#ifdef LIGHT_KDF_RPMB_KEY
+ /* Step1: retrive RPMB key from KDF function */
+ ret = csi_kdf_gen_hmac_key(kdf_rpmb_key, &kdf_rpmb_key_length);
+ if (ret != 0) {
+ return -1;
+ }
+ /* Make sure rpmb key length must be 32*/
+ if (kdf_rpmb_key_length != 32) {
+ return -1;
+ }
+
+ temp_rpmb_key_addr = (unsigned long *)kdf_rpmb_key;
+
+ /* Step2: check whether RPMB key is available */
+ sprintf(runcmd, "mmc rpmb read 0x%lx 0 1 0x%lx", (unsigned long)blkdata, (unsigned long)temp_rpmb_key_addr);
+ ret = run_command(runcmd, 0);
+ if (ret == CMD_RET_SUCCESS) {
+ return -1;
+ }
+
+ /* Step3: Write RPMB key at once */
+ sprintf(runcmd, "mmc rpmb key 0x%lx", (unsigned long)temp_rpmb_key_addr);
+ ret = run_command(runcmd, 0);
+ if (ret != CMD_RET_SUCCESS) {
+ return -1;
+ }
+ return 0;
+#else
+ return 1;
+#endif
+}
+
int csi_tf_get_image_version(unsigned int *ver)
{
char runcmd[64] = {0};
return 0;
}
+int csi_kernel_get_image_version(unsigned int *ver)
+{
+ char runcmd[64] = {0};
+ unsigned char blkdata[256];
+
+ /* kernel version reside in RPMB block#0, offset#32*/
+ sprintf(runcmd, "mmc rpmb read 0x%lx 0 1", (unsigned long)blkdata);
+ run_command(runcmd, 0);
+ *ver = (blkdata[32] << 8) + blkdata[33];
+
+ return 0;
+}
+
int csi_tee_set_image_version(unsigned int ver)
{
char runcmd[64] = {0};
printf("Get tee img version fail\n");
return CMD_RET_FAILURE;
}
+ } else if (strcmp(imgname, KERNEL_PART_NAME) == 0){
+
+ ret = csi_kernel_get_image_version(&cur_img_version);
+ if (ret != 0) {
+ printf("Get kernel img version fail\n");
+ return CMD_RET_FAILURE;
+ }
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
ret = csi_uboot_get_image_version(&cur_img_version);
if (ret != 0) {
if (ret != 0) {
return CMD_RET_FAILURE;
}
+ } else if (strcmp(imgname, KERNEL_PART_NAME) == 0) {
+ ret = verify_customer_image(T_KRLIMG, vimage_addr);
+ if (ret != 0) {
+ return CMD_RET_FAILURE;
+ }
} else if (strcmp(imgname, UBOOT_PART_NAME) == 0) {
ret = verify_customer_image(T_UBOOT, vimage_addr);
if (ret != 0) {
int ret = 0;
unsigned long tf_addr = LIGHT_TF_FW_ADDR;
unsigned long tee_addr = LIGHT_TEE_FW_ADDR;
+ unsigned long kernel_addr = LIGHT_KERNEL_ADDR;
unsigned int tf_image_size = 0;
unsigned int tee_image_size = 0;
+ unsigned int kernel_image_size = 0;
printf("\n\n");
printf("Now, we start to verify all trust firmware before boot kernel !\n");
+ /* Enject RPMB KEY directly in startup */
+ csi_rpmb_write_access_key();
+
/* Initialize secure basis of functions */
ret = csi_sec_init();
if (ret != 0) {
return CMD_RET_FAILURE;
#endif
}
+
+ // /* Step3. Check and verify light kernel image */
+ // if (image_have_head(kernel_addr) == 1) {
+ // printf("Process kernel image verification ...\n");
+ // ret = verify_customer_image(T_KRLIMG, kernel_addr);
+ // if (ret != 0) {
+ // return CMD_RET_FAILURE;
+ // }
+
+ // kernel_image_size = get_image_size(kernel_addr);
+ // printf("Kernel image size: %d\n", kernel_image_size);
+ // if (kernel_image_size < 0) {
+ // printf("GET kernel image size error\n");
+ // return CMD_RET_FAILURE;
+ // }
+
+ // memmove((void *)kernel_addr, (const void *)(kernel_addr + HEADER_SIZE), kernel_image_size);
+ // } else {
+ // #ifndef LIGHT_NON_COT_BOOT
+ // return CMD_RET_FAILURE;
+ // #endif
+ // }
+
return 0;
}
#define VOSYS_SYSREG_BASE (0xffef528000)
#define VOSYS_CLK_GATE_REG (VOSYS_SYSREG_BASE + 0x50)
#define VOSYS_CLK_GATE1_REG (VOSYS_SYSREG_BASE + 0x54)
+#define VOSYS_DPU_CCLK_CFG (VOSYS_SYSREG_BASE + 0x64)
+
+/* VISYS_SYSREG_R */
+#define VISYS_SYSREG_BASE (0xffe4040000)
+#define VISYS_MIPI_CSI0_PIXELCLK (VISYS_SYSREG_BASE + 0x30)
+#define VISYS_ISP0_CLK_CFG (VISYS_SYSREG_BASE + 0x24)
+#define VISYS_ISP1_CLK_CFG (VISYS_SYSREG_BASE + 0x28)
+#define VISYS_ISP_RY_CLK_CFG (VISYS_SYSREG_BASE + 0x2c)
+
+/* APSYS_SYSREG_R */
+#define APSYS_CLKGEN_BASE (0xffef010000)
+#define APSYS_DPU0_PLL_DIV_CFG (APSYS_CLKGEN_BASE + 0x1e8)
+#define APSYS_DPU1_PLL_DIV_CFG (APSYS_CLKGEN_BASE + 0x1ec)
/* AP_DPU0_PLL_CFG1 */
#define AP_DPU0_PLL_RST BIT(29)
/* VOSYS_CLK_GATE1_REG */
#define CLKCTRL_HDMI_PIXCLK_EN BIT(0)
+/* VOSYS_DPU_CCLK_CFG */
+#define VOSYS_DPU_CCLK_DIV_NUM_MASK 0xf
+#define VOSYS_DPU_CCLK_DIV_NUM_SHIFT 0
+#define VOSYS_DPU_CCLK_DIV_EN BIT(4)
+
+/* VISYS_MIPI_CSI0_PIXELCLK */
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT 0
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK 0xf
+#define VISYS_MIPI_CSI0_PIXELCLK_DIV_EN BIT(4)
+
+/* VISYS_ISP0_CLK_CFG */
+#define VISYS_ISP0_CLK_DIV_EN BIT(4)
+#define VISYS_ISP0_CLK_DIV_NUM_SHIFT (0)
+#define VISYS_ISP0_CLK_DIV_NUM_MASK 0xf
+
+/* VISYS_ISP1_CLK_CFG */
+#define VISYS_ISP1_CLK_DIV_EN BIT(4)
+#define VISYS_ISP1_CLK_DIV_NUM_SHIFT (0)
+#define VISYS_ISP1_CLK_DIV_NUM_MASK 0xf
+
+/* VISYS_ISP_RY_CLK_CFG */
+#define VISYS_ISP_RY_CLK_DIV_EN BIT(4)
+#define VISYS_ISP_RY_CLK_DIV_NUM_SHIFT (0)
+#define VISYS_ISP_RY_CLK_DIV_NUM_MASK 0xf
+
+/* APSYS_DPU0_PLL_DIV_CFG */
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_EN BIT(8)
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK 0xff
+#define APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT 0
+
+/* APSYS_DPU1_PLL_DIV_CFG */
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_EN BIT(8)
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK 0xff
+#define APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT 0
+
+enum multimedia_div_type {
+ VI_MIPI_CSI0_DIV,
+ VI_ISP0_CORE_DIV,
+ VI_ISP1_CORE_DIV,
+ VI_ISP_RY_CORE_DIV,
+ VO_DPU_CORE_DIV,
+ VO_DPU_PLL0_DIV,
+ VO_DPU_PLL1_DIV,
+};
+
#define C910_CCLK 0
#define C910_CCLK_I0 1
#define CLK_END 16
LIGHT_PLL_RATE(3000000000U, 1000000000U, 1, 125, 0, 3, 1),
LIGHT_PLL_RATE(3000000000U, 1500000000U, 1, 125, 0, 2, 1),
LIGHT_PLL_RATE(1800000000U, 1800000000U, 1, 75, 0, 1, 1),
+ LIGHT_PLL_RATE(2256000000U, 752000000U, 1, 94, 0, 3, 1),
+ LIGHT_PLL_RATE(3000000000U, 300000000U, 1, 125, 0, 5, 2),
+ LIGHT_PLL_RATE(1848000000U, 1848000000U, 1, 77, 0, 1, 1),
+ LIGHT_PLL_RATE(1872000000U, 1872000000U, 1, 78, 0, 1, 1),
};
static const struct light_pll_rate_table light_audio_pll_tbl[] = {
enum clk_device_type clk_dev_type;
};
-struct clk_info {
- const char *clk_name;
- enum clk_device_type clk_dev_type;
-};
-
static const struct clk_info c910_cclk_sels[] = {
{"c910_cclk_i0", CLK_DEV_MUX},
{"cpu_pll1_foutpostdiv", CLK_DEV_PLL},
if (!strcmp(clk->clk_name, parent))
return 0;
- printf("clk->num_parents = %d\n", clk->num_parents);
+ debug("clk->num_parents = %d\n", clk->num_parents);
for (i = 0; i < clk->num_parents; i++) {
pr_debug("parent%d:%s\n", i, clk->parents[i].clk_name);
{
unsigned int clk_cfg;
-#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
+#if (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || (defined CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || (defined CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
clk_cfg = readl((void __iomem *)AP_PERI_CLK_CFG);
clk_cfg &= ~(GMAC1_CLK_EN);
writel(clk_cfg, (void __iomem *)AP_PERI_CLK_CFG);
writel(cfg1, (void __iomem *)AP_DPU1_PLL_CFG1);
}
+static void ap_multimedia_div_num_set(enum multimedia_div_type type, unsigned int div_num)
+{
+ unsigned long div_reg;
+ unsigned int div_num_shift, div_num_mask, div_en;
+ unsigned int div_cfg;
+
+ switch (type) {
+ case VI_MIPI_CSI0_DIV:
+ div_reg = VISYS_MIPI_CSI0_PIXELCLK;
+ div_num_shift = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_SHIFT;
+ div_num_mask = VISYS_MIPI_CSI0_PIXELCLK_DIV_NUM_MASK;
+ div_en = VISYS_MIPI_CSI0_PIXELCLK_DIV_EN;
+ break;
+ case VI_ISP0_CORE_DIV:
+ div_reg = VISYS_ISP0_CLK_CFG;
+ div_num_shift = VISYS_ISP0_CLK_DIV_NUM_SHIFT;
+ div_num_mask = VISYS_ISP0_CLK_DIV_NUM_MASK;
+ div_en = VISYS_ISP0_CLK_DIV_EN;
+ break;
+ case VI_ISP1_CORE_DIV:
+ div_reg = VISYS_ISP1_CLK_CFG;
+ div_num_shift = VISYS_ISP1_CLK_DIV_NUM_SHIFT;
+ div_num_mask = VISYS_ISP1_CLK_DIV_NUM_MASK;
+ div_en = VISYS_ISP1_CLK_DIV_EN;
+ break;
+ case VI_ISP_RY_CORE_DIV:
+ div_reg = VISYS_ISP_RY_CLK_CFG;
+ div_num_shift = VISYS_ISP_RY_CLK_DIV_NUM_SHIFT;
+ div_num_mask = VISYS_ISP_RY_CLK_DIV_NUM_MASK;
+ div_en = VISYS_ISP_RY_CLK_DIV_EN;
+ break;
+ case VO_DPU_CORE_DIV:
+ div_reg = VOSYS_DPU_CCLK_CFG;
+ div_num_shift = VOSYS_DPU_CCLK_DIV_NUM_SHIFT;
+ div_num_mask = VOSYS_DPU_CCLK_DIV_NUM_MASK;
+ div_en = VOSYS_DPU_CCLK_DIV_EN;
+ break;
+ case VO_DPU_PLL0_DIV:
+ div_reg =APSYS_DPU0_PLL_DIV_CFG;
+ div_num_shift = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_SHIFT;
+ div_num_mask = APSYS_DPU0_PLL_DIV_CLK_DIV_NUM_MASK;
+ div_en = APSYS_DPU0_PLL_DIV_CLK_DIV_EN;
+ break;
+ case VO_DPU_PLL1_DIV:
+ div_reg =APSYS_DPU1_PLL_DIV_CFG;
+ div_num_shift = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_SHIFT;
+ div_num_mask = APSYS_DPU1_PLL_DIV_CLK_DIV_NUM_MASK;
+ div_en = APSYS_DPU1_PLL_DIV_CLK_DIV_EN;
+ break;
+ default:
+ printf("invalid ap multimedia divider type\n");
+ return;
+ }
+
+ div_cfg = readl((void __iomem *)div_reg);
+ div_cfg &= ~div_en;
+ writel(div_cfg, (void __iomem *)div_reg);
+
+ div_cfg &= ~(div_num_mask << div_num_shift);
+ div_cfg |= (div_num & div_num_mask) << div_num_shift;
+ div_cfg |= div_en;
+ writel(div_cfg, (void __iomem *)div_reg);
+}
+
int clk_config(void)
{
unsigned long rate = clk_light_get_rate("c910_cclk", CLK_DEV_MUX);
if (ret)
return ret;
#endif
+
+ /* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+ ap_multimedia_div_num_set(VI_MIPI_CSI0_DIV, 12); /* Input frquency: 2376MHZ */
+ ap_multimedia_div_num_set(VI_ISP0_CORE_DIV, 15); /* Input frquency: 2376MHZ */
+ ap_multimedia_div_num_set(VI_ISP1_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+ ap_multimedia_div_num_set(VI_ISP_RY_CORE_DIV, 12); /* Input frquency: 2376MHZ */
+ ap_multimedia_div_num_set(VO_DPU_CORE_DIV, 4); /* Input frquency: 2376MHZ */
+ ap_multimedia_div_num_set(VO_DPU_PLL0_DIV, 16);
+ ap_multimedia_div_num_set(VO_DPU_PLL1_DIV, 4);
+#endif
ap_hdmi_clk_endisable(false);
ap_mipi_dsi1_clk_endisable(false);
--- /dev/null
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define LIGHT_TEE_SYSREG_BASE ((void __iomem*)0xffff200000)
+#define REG_SECURITY_ERR_3 (LIGHT_TEE_SYSREG_BASE + 0x30)
+
+/* id: 0~8 */
+#define DS_C910_BASE(id) (0xffffc57000 + (id) * 0x40)
+#define DS_APB_BASE(id) (0xffff270000 + ((id) - 4) * 0x1000)
+
+#define DS_BASE(id) (((id) > 3) ? (DS_APB_BASE(id)) : (DS_C910_BASE(id)))
+
+#define REG_HW_VERSION(id) ((void __iomem *)DS_BASE(id) + 0x00) //RO
+#define REG_SENSOR_ALARM(id) ((void __iomem *)DS_BASE(id) + 0x04) //RO
+#define REG_HEALTH_TEST_ALARM(id) ((void __iomem *)DS_BASE(id) + 0x08) //RO
+#define REG_HEALTH_TEST_STATUS(id) ((void __iomem *)DS_BASE(id) + 0x0C) //RO
+#define REG_CONTROL(id) ((void __iomem *)DS_BASE(id) + 0x10) //WO
+#define REG_IRQ_STATUS(id) ((void __iomem *)DS_BASE(id) + 0x14) //RO
+#define REG_IRQ_CLEAR(id) ((void __iomem *)DS_BASE(id) + 0x18) //WO
+#define REG_IRQ_CONFIG(id) ((void __iomem *)DS_BASE(id) + 0x1C) //RW
+#define REG_STATUS_DSX(id, x) ((void __iomem *)DS_BASE(id) + 0x20 + 0x04 * x) //RO
+
+#define LIGHT_SEC_IRQ_NUM 91
+
+#define MAX_DIGITAL_SENSOR_NUM 9
+#define MAX_HW_MACRO_NUM_PER_DS 16
+
+#define DS_HW_MACRO_TL_MASK 0xffff
+
+#define DS_INVALID_MACRO_ID MAX_HW_MACRO_NUM_PER_DS
+
+#define DS_1_ERR BIT(16) //digital_sensor_C910_0 ~ digital_sensor_C910_3
+#define DS_3_ERR BIT(18) //digital_sensor_apb_3
+#define DS_4_ERR BIT(19) //digital_sensor_apb_4
+#define DS_5_ERR BIT(20) //digital_sensor_apb_5
+#define DS_6_ERR BIT(21) //digital_sensor_apb_6
+#define DS_7_ERR BIT(22) //digital_sensor_apb_7
+#define DS_ERR (DS_1_ERR | DS_3_ERR | DS_4_ERR | DS_5_ERR | DS_6_ERR | DS_7_ERR)
+
+#define CFG_DS_CPU_THREAT_LEVEL 0
+#define CFG_APB0_THREAT_LEVEL 0
+#define CFG_APB1_THREAT_LEVEL 0
+
+#define AONSYS_RSTGEN_BASE ((void __iomem *)0xFFFFF44000UL)
+#define REG_SYS_RST_CFG (AONSYS_RSTGEN_BASE + 0x10)
+#define SW_SYS_RST_REQ (1 << 0)
+#define REG_RST_REQ_EN_0 (AONSYS_RSTGEN_BASE + 0x140)
+#define SW_GLB_RST_EN (1 << 0)
+
+struct ds_data {
+ int id;
+ u32 hw_macro_num;
+};
+
+struct ds_data ds_array[MAX_DIGITAL_SENSOR_NUM] = {
+ {0, 4}, //digital_sensor_C910_0
+ {1, 4}, //digital_sensor_C910_1
+ {2, 4}, //digital_sensor_C910_2
+ {3, 4}, //digital_sensor_C910_3
+ {4, 16}, //digital_sensor_apb_3
+ {5, 11}, //digital_sensor_apb_4
+ {6, 4}, //digital_sensor_apb_5
+ {7, 16}, //digital_sensor_apb_6
+ {8, 8}, //digital_sensor_apb_7
+};
+
+static void system_reset(void)
+{
+ u32 data = readl(REG_RST_REQ_EN_0);
+
+ /* global reset enable */
+ data |= SW_GLB_RST_EN;
+ writel(data, REG_RST_REQ_EN_0);
+
+ /* global reset request */
+ writel(SW_SYS_RST_REQ, REG_SYS_RST_CFG);
+ mdelay(1000);
+}
+
+static u32 ds_hw_macro_threat_level_get(int ds_id, u32 macro_id)
+{
+ return readl(REG_STATUS_DSX(ds_id, macro_id)) & DS_HW_MACRO_TL_MASK;
+}
+
+static __maybe_unused int ds_health_test_done_status(int ds_id, u32 macro_id)
+{
+ return readl(REG_HEALTH_TEST_STATUS(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused int ds_health_test_alarm_status(int ds_id, u32 macro_id)
+{
+ return readl(REG_HEALTH_TEST_ALARM(ds_id)) & (1 << macro_id) ? 1 : 0;
+}
+
+static __maybe_unused bool ds_sensor_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+ u32 alarm_status = readl(REG_SENSOR_ALARM(ds_id));
+ int num = ds_array[ds_id].hw_macro_num;
+ int s_alarm_bit = 0, j = 0;
+ bool sensor_alarm_event_occured = false;
+
+ for (int i = 0; i < num; i++) {
+ s_alarm_bit = 1 << i;
+ if (alarm_status & s_alarm_bit) {
+ event_macro[j] = i;
+ j++;
+ sensor_alarm_event_occured = true;
+ }
+ }
+
+ return sensor_alarm_event_occured;
+}
+
+static __maybe_unused bool ds_health_alarm_event_hw_macro_get(int ds_id, u32 *event_macro)
+{
+ u32 h_alarm_status = readl(REG_HEALTH_TEST_ALARM(ds_id));
+ int num = ds_array[ds_id].hw_macro_num;
+ int h_alarm_bit = 0, j = 0;
+ bool health_alarm_event_occured = false;
+
+ for (int i = 0; i < num; i++) {
+ h_alarm_bit = 1 << i;
+ if (h_alarm_status & h_alarm_bit) {
+ event_macro[j] = i;
+ j++;
+ health_alarm_event_occured = true;
+ }
+ }
+
+ return health_alarm_event_occured;
+}
+
+static bool ds_sensor_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+ u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+ int num = ds_array[ds_id].hw_macro_num;
+ int s_alarm_bit = 0, j = 0;
+ bool sensor_alarm_irq_occured = false;
+
+ for (int i = 0; i < num; i++) {
+ s_alarm_bit = 1 << ((i << 1) + 1);
+ if (irq_status & s_alarm_bit) {
+ irq_macro[j] = i;
+ debug("[%s,%d]irq_macro[%d] = %d\n", __func__, __LINE__,
+ j, irq_macro[j]);
+ j++;
+ sensor_alarm_irq_occured = true;
+ }
+ }
+
+ debug("[%s,%d] sensor_alarm_irq_occured = %d\n", __func__, __LINE__,
+ sensor_alarm_irq_occured);
+ return sensor_alarm_irq_occured;
+}
+
+static __maybe_unused bool ds_health_irq_hw_macro_get(int ds_id, u32 *irq_macro)
+{
+ u32 irq_status = readl(REG_IRQ_STATUS(ds_id));
+ int num = ds_array[ds_id].hw_macro_num;
+ int h_alarm_bit = 0, j = 0;
+ bool health_alarm_irq_occured = false;
+
+ for (int i = 0; i < num; i++) {
+ h_alarm_bit = 1 << (i << 1);
+ if (irq_status & h_alarm_bit) {
+ irq_macro[j] = i;
+ j++;
+ health_alarm_irq_occured = true;
+ }
+ }
+
+ return health_alarm_irq_occured;
+}
+
+static void ds_sensor_irq_clear(int ds_id, u32 macro_id)
+{
+ int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+
+ debug("[%s,%d]reg: 0x%lx, s_alarm_bit = 0x%x\n", __func__, __LINE__,
+ (unsigned long)REG_IRQ_CLEAR(ds_id), s_alarm_bit);
+
+ writel(s_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static __maybe_unused void ds_health_irq_clear(int ds_id, u32 macro_id)
+{
+ int h_alarm_bit = 1 << (macro_id << 1);
+
+ writel(h_alarm_bit, REG_IRQ_CLEAR(ds_id));
+}
+
+static void ds_hw_macro_sensor_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+ int s_alarm_bit = 1 << ((macro_id << 1) + 1);
+ u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+ if (en)
+ bitmap |= s_alarm_bit;
+ else
+ bitmap &= ~s_alarm_bit;
+
+ writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_alarm_endisable(int ds_id, u32 macro_id, bool en)
+{
+ int h_alarm_bit = 1 << (macro_id << 1);
+ u32 bitmap = readl(REG_IRQ_CONFIG(ds_id));
+
+ if (en)
+ bitmap |= h_alarm_bit;
+ else
+ bitmap &= ~h_alarm_bit;
+
+ writel(bitmap, REG_IRQ_CONFIG(ds_id));
+}
+
+static void ds_hw_macro_rearm(int ds_id, u32 macro_id, int macro_size)
+{
+ int rearm_bit = 1 << (macro_id + macro_size);
+
+ debug("[%s,%d]rearm_bit = 0x%x\n", __func__, __LINE__, rearm_bit);
+ writel(rearm_bit, REG_CONTROL(ds_id));
+}
+
+static __maybe_unused void ds_hw_macro_health_test_start(int ds_id, u32 macro_id)
+{
+ int start_bit = 1 << macro_id;
+
+ writel(start_bit, REG_CONTROL(ds_id));
+}
+
+static void light_sec_irq_handler(void)
+{
+ u32 id, i, j = 0, t = 0, size;
+ u32 tl;
+ u32 irq_macro[MAX_HW_MACRO_NUM_PER_DS] = {0};
+ u32 apb_ds[8] = {0};
+ u32 status = readl(REG_SECURITY_ERR_3);
+
+ if (!status)
+ return;
+
+ if (!(status & DS_ERR)) {
+ printf("Unexpected security interrupt but not ditital sensor alarm occured\n");
+ return; //drop other security interrupts, how to clear ?
+ }
+
+ if (status & DS_1_ERR) {
+ printf("C910 cpu digital sensor detect error event\n");
+
+ for (id = 0; id < 4; id++) {
+ for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+ irq_macro[i] = DS_INVALID_MACRO_ID;
+
+ if (!ds_sensor_irq_hw_macro_get(id, irq_macro))
+ continue;
+
+ size = ds_array[id].hw_macro_num;
+
+ i = 0;
+ while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {
+
+ tl = ds_hw_macro_threat_level_get(id, irq_macro[i]);
+
+ printf("DS%d-MACRO%d Threat Level: 0x%x\n", id, irq_macro[i], tl);
+
+ if (tl >= CFG_DS_CPU_THREAT_LEVEL) {
+#if 0
+ run_command("ds_cpu_alarm 1500000000", 0);
+#else
+ system_reset();
+#endif
+ } else {
+#if 0
+ run_command("ds_cpu_alarm 1500000000", 0);
+#else
+ system_reset();
+#endif
+ }
+
+ //Fixmed: before irq clear !!!
+ ds_hw_macro_rearm(id, irq_macro[i], size);
+
+ ds_sensor_irq_clear(id, irq_macro[i]);
+
+ i++;
+ }
+ }
+ }
+
+ if (status & DS_3_ERR) {
+ printf("apb digital sensor3 detect error event\n");
+ apb_ds[j++] = 4;
+ }
+
+ if (status & DS_4_ERR) {
+ printf("apb digital sensor4 detect error event\n");
+ apb_ds[j++] = 5;
+ }
+
+ if (status & DS_5_ERR) {
+ printf("apb digital sensor5 detect error event\n");
+ apb_ds[j++] = 6;
+ }
+
+ if (status & DS_6_ERR) {
+ printf("apb digital sensor6 detect error event\n");
+ apb_ds[j++] = 7;
+ }
+
+ if (status & DS_7_ERR) {
+ printf("apb digital sensor7 detect error event\n");
+ apb_ds[j++] = 8;
+ }
+
+
+ while (apb_ds[t]) {
+ if (apb_ds[t] < 4 || apb_ds[t] > 8) {
+ printf("invalid digial sensor id(%d)\n", apb_ds[t]);
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(irq_macro); i++)
+ irq_macro[i] = DS_INVALID_MACRO_ID;
+
+ size = ds_array[apb_ds[t]].hw_macro_num;
+
+ if (ds_sensor_irq_hw_macro_get(apb_ds[t], irq_macro)) {
+
+ i = 0;
+ while (i < MAX_HW_MACRO_NUM_PER_DS && irq_macro[i] != DS_INVALID_MACRO_ID) {//hardware macro
+
+ debug("[%s,%d]irq_status = 0x%x, alarm_status = 0x%x\n", __func__, __LINE__,
+ readl(REG_IRQ_STATUS(apb_ds[t])), readl(REG_SENSOR_ALARM(apb_ds[t])));
+
+ tl = ds_hw_macro_threat_level_get(apb_ds[t], irq_macro[i]);
+ if (tl)
+ printf("DS%d-MACRO%d Threat Level: 0x%x\n", apb_ds[t], irq_macro[i], tl);
+
+ if (apb_ds[t] == 8 && tl >= CFG_APB1_THREAT_LEVEL) {
+ //handle1
+ run_command("ds_3to6_alarm 4", 0);
+ } else if (tl >= CFG_APB0_THREAT_LEVEL) {
+ //handle2
+ run_command("ds_3to6_alarm 4", 0);
+ } else {
+ //handle3
+ run_command("ds_3to6_alarm 4", 0);
+ }
+
+ //Fixmed: before irq clear !!!
+ ds_hw_macro_rearm(apb_ds[t], irq_macro[i], size);
+
+ ds_sensor_irq_clear(apb_ds[t], irq_macro[i]);
+
+ i++;
+ }
+ }
+
+ t++; //digital number
+ }
+}
+
+static int ds_platform_init(void)
+{
+ int ds_id, macro_id, ret = 0;
+
+ for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+
+ printf("Digital Sensor%d HW Version: 0x%x\n", ds_id, readl(REG_HW_VERSION(ds_id)));
+
+ for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++) {
+ ds_hw_macro_sensor_alarm_endisable(ds_id,
+ macro_id, true);
+ ds_hw_macro_health_test_start(ds_id, macro_id);
+ udelay(5);
+ ret = ds_health_test_done_status(ds_id, macro_id);
+ if (!ret) {
+ printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+ ds_hw_macro_sensor_alarm_endisable(ds_id,
+ macro_id, false);
+ } else {
+ ret = ds_health_test_alarm_status(ds_id, macro_id);
+ if (ret) {
+ ds_hw_macro_sensor_alarm_endisable(ds_id,
+ macro_id, false);
+ printf("health test failed for DS%d-Macro%d\n", ds_id, macro_id);
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int ds_sec_interrupt_init(void)
+{
+ int ret;
+
+ ret = irq_handler_register(LIGHT_SEC_IRQ_NUM, light_sec_irq_handler);
+ if (ret) {
+ printf("failed to register security interrupt handler\n");
+ return ret;
+ }
+
+ irq_priority_set(LIGHT_SEC_IRQ_NUM);
+ irq_enable(LIGHT_SEC_IRQ_NUM);
+
+ return 0;
+}
+
+void ds_uninit(void)
+{
+ int ds_id, macro_id;
+
+ irq_disable(LIGHT_SEC_IRQ_NUM);
+
+ for (ds_id = 0; ds_id < MAX_DIGITAL_SENSOR_NUM; ds_id++) {
+ for (macro_id = 0; macro_id < ds_array[ds_id].hw_macro_num; macro_id++)
+ ds_hw_macro_sensor_alarm_endisable(ds_id, macro_id, false);
+ }
+
+ irq_handler_register(LIGHT_SEC_IRQ_NUM, NULL);
+}
+
+int ds_init(void)
+{
+ int ret;
+
+ ds_platform_init();
+
+ ret = ds_sec_interrupt_init();
+ if (ret)
+ return ret;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2017-2022 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+#include <thead/clock_config.h>
+
+#define TEE_LIGHT_APCLK_ADDRBASE ((void __iomem *)0xffff011000)
+#define REG_TEESYS_CLK_TEECFG ((void __iomem *)TEE_LIGHT_APCLK_ADDRBASE + 0x1cc)
+
+/* VIDEO PLL */
+#define TEESYS_I1_HCLK_DIV_EN BIT(12)
+#define TEESYS_I1_HCLK_DIV_NUM_SHIFT 8
+#define TEESYS_I1_HCLK_DIV_NUM_MASK 0xf
+
+#define LIGHT_CPUFREQ_THRE 1500000
+#define LIGHT_C910_BUS_CLK_SYNC BIT(11)
+#define LIGHT_C910_BUS_CLK_RATIO_MASK 0x700
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_2 0x100
+#define LIGHT_C910_BUS_CLK_DIV_RATIO_3 0x200
+
+extern int ds_init(void);
+
+bool global_ds_init = false;
+
+static int ds_cpu_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned long new_freq;
+ int ret = 0;
+ u32 val;
+ const struct clk_info *parent;
+
+ if (argc != 2) {
+ printf("invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (strict_strtoul(argv[1], 10, &new_freq) < 0)
+ return CMD_RET_USAGE;
+
+ val = readl(TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+ val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
+ val |= LIGHT_C910_BUS_CLK_DIV_RATIO_3;
+
+ writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+ val &= ~LIGHT_C910_BUS_CLK_SYNC;
+ writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+ udelay(1);
+ val |= LIGHT_C910_BUS_CLK_SYNC;
+ writel(val, TEE_LIGHT_APCLK_ADDRBASE + 0x100);
+ udelay(1);
+
+ printf("wait for cpu frequency alarm, rate: %ld\n", new_freq);
+
+ parent = clk_light_get_parent("c910_cclk");
+ if (!strcmp(parent->clk_name, "cpu_pll1_foutpostdiv")) {
+ ret = clk_light_set_rate("c910_cclk_i0", CLK_DEV_MUX, new_freq);
+ if (ret) {
+ printf("failed to set cpu frequency\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ udelay(3);
+ ret = clk_light_set_parent("c910_cclk", "c910_cclk_i0");
+ if (ret) {
+ printf("failed to set parent clock for cpu\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ } else {
+ ret = clk_light_set_rate("cpu_pll1_foutpostdiv", CLK_DEV_PLL, new_freq);
+ if (ret) {
+ printf("failed to set cpu frequency\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ udelay(3);
+ ret = clk_light_set_parent("c910_cclk", "cpu_pll1_foutpostdiv");
+ if (ret) {
+ printf("failed to set parent clock for cpu\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
+ printf("C910 CPU FREQ: %ldMHz\n", new_freq / 1000000);
+
+out:
+ return ret;
+}
+
+static int ds_3to6_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned long div;
+ int ret = 0;
+ u32 cfg;
+
+ if (argc != 2) {
+ printf("invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (strict_strtoul(argv[1], 10, &div) < 0)
+ return CMD_RET_USAGE;
+
+ if (div < 2 || div > 15) {
+ printf("invalid teesys clock divider number(%ld)\n", div);
+ return -EINVAL;
+ }
+
+ cfg = readl(REG_TEESYS_CLK_TEECFG);
+ cfg &= ~TEESYS_I1_HCLK_DIV_EN;
+ writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+ cfg &= ~(TEESYS_I1_HCLK_DIV_NUM_MASK << TEESYS_I1_HCLK_DIV_NUM_SHIFT);
+ cfg |= (div & TEESYS_I1_HCLK_DIV_NUM_MASK) << TEESYS_I1_HCLK_DIV_NUM_SHIFT;
+ cfg |= TEESYS_I1_HCLK_DIV_EN;
+ writel(cfg, REG_TEESYS_CLK_TEECFG);
+
+ return ret;
+}
+
+static int ds_7_alarm_clk_set(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return ds_3to6_alarm_clk_set(cmdtp, flag, argc, argv);
+}
+
+static int ds_init_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (!global_ds_init) {
+ global_ds_init = true;
+ return ds_init();
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(ds_init, 1, 0, ds_init_cfg, "ds_init", "Initalize the digital sensor controller");
+U_BOOT_CMD(ds_cpu_alarm, 2, 0, ds_cpu_alarm_clk_set, "ds_cpu_alarm 1500000000", "digital sensor cpu0~cpu3 alarm test");
+U_BOOT_CMD(ds_3to6_alarm, 2, 0, ds_3to6_alarm_clk_set, "ds_3to6_alarm 3", "digital sensor for digital3~digital6 alarm test");
+U_BOOT_CMD(ds_7_alarm, 2, 0, ds_7_alarm_clk_set, "ds_7_alarm 3", "digital sensor for digital7 alarm test");
+
*/
#include <common.h>
+#include <command.h>
#include <asm/io.h>
#include <asm/types.h>
#include <thead/clock_config.h>
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
-#elif defined ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+#elif defined ( CONFIG_TARGET_LIGHT_FM_C910_VAL_B) || defined ( CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
static void light_iopin_init(void)
{
/* aon-padmux config */
light_pin_mux(AOGPIO_12,1);
light_pin_mux(AOGPIO_13,1);
light_pin_mux(AOGPIO_14,0);
+ light_pin_cfg(AOGPIO_14,PIN_SPEED_NORMAL,PIN_PU,2); ///WL_DEV_WAKE_HOST
light_pin_mux(AOGPIO_15,0);
+ light_pin_cfg(AOGPIO_15,PIN_SPEED_NORMAL,PIN_PU,2); ///BT_DEV_WAKE_HOST
+
+ light_pin_mux(AUDIO_PA4,3); ///NC
+ light_pin_cfg(AUDIO_PA4,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_mux(AUDIO_PA5,3); ///NC
+ light_pin_cfg(AUDIO_PA5,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_mux(AUDIO_PA11,3); ///NC
+ light_pin_cfg(AUDIO_PA11,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_mux(AUDIO_PA16,3); ///NC
+ light_pin_cfg(AUDIO_PA16,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA9,3);
light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);// reset signal for audio-pa
- light_pin_mux(AUDIO_PA10,3);
- light_pin_mux(AUDIO_PA12,3);
+ light_pin_mux(AUDIO_PA10,3); ///NC
+ light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_mux(AUDIO_PA12,3); ///NC
+ light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AUDIO_PA13,0);
/*ap-padmux on left/top */
light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+ light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8);
+ light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(GPIO0_30,0);
light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dovdd18_ir_reg
- light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PD,2);//soc_avdd25_ir_reg
- light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dvdd12_ir_reg
+ light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dovdd18_ir_reg
+ light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2);//soc_avdd25_ir_reg
+ light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dvdd12_ir_reg
light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);//soc_vdd_3v3_en_reg for uart/gmac/debug_port/hdmi/sd
light_pin_mux(GPIO1_0,1);
light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PD,2); //soc_vdd18_lcd0_en_reg --backup regulator
- light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PU,2);//soc_lcd0_bias_en_reg
+#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+ light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); //soc_vdd18_lcd0_en_reg --backup regulator
+#else
+ light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2); //soc_vdd18_lcd0_en_reg
+#endif
+ light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2);//soc_lcd0_bias_en_reg
light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PD,2);//reg_tp_pwr_en --touch pannel
- light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dovdd18_rgb_reg
- light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PD,2);//soc_dvdd12_rgb_reg
- light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PD,2);//soc_avdd28_rgb_reg
+#ifndef defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+ light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2);//reg_tp_pwr_en --touch pannel
+#else
+ light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);//reg_tp_pwr_en --touch pannel
+#endif
+ light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dovdd18_rgb_reg
+ light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2);//soc_dvdd12_rgb_reg
+ light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2);//soc_avdd28_rgb_reg
light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(CLK_OUT_1,1);
light_pin_mux(CLK_OUT_2,3);
light_pin_mux(CLK_OUT_3,1);
- light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);///volume key
/*ap-pdmux on righ/top*/
light_pin_mux(QSPI0_SCLK,2);
light_pin_mux(SPI_MOSI,3);
light_pin_mux(SPI_MISO,3);
light_pin_mux(SPI_SCLK,3);
- light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2); ///vdd5v_se_en
light_pin_mux(GPIO2_18,0);
light_pin_mux(GPIO2_19,0);
light_pin_mux(GPIO2_20,0);
light_pin_mux(GPIO2_21,0);
light_pin_mux(GPIO2_22,0);
+ light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2); ///WL_HOST_WAKE_DEV
light_pin_mux(GPIO2_23,0);
+ light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2); ///BT_DEV_WAKE_HOST
light_pin_mux(GPIO2_24,0);
light_pin_mux(GPIO2_25,0);
light_pin_mux(SDIO0_WPRTN,3);
- light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2);///NC
light_pin_mux(SDIO1_WPRTN,3);
- light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);//wcn33_en
+ light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PD,2);//gpio2_28 vbus_en
light_pin_mux(SDIO1_DETN,3);
- light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2); //se_5v_en
+ light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2); //gpio2_29 wcn33_en
light_pin_mux(GPIO2_30,0);
light_pin_mux(GPIO2_31,0);
light_pin_mux(GPIO3_0,0);
light_pin_mux(GPIO3_1,0);
light_pin_mux(GPIO3_2,1);
- light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PD, 0x2);//soc_avdd28_scan_en_reg
- light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PD, 0x2);//soc_dovdd18_scan_reg
- light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PD, 0x2); //soc_dvdd12_scan_reg
+ light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2);//soc_avdd28_scan_en_reg
+ light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2);//soc_dovdd18_scan_reg
+ light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2); //soc_dvdd12_scan_reg
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
/* aon-padmux config */
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
+ light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AOGPIO_9,3);
light_pin_mux(AOGPIO_10,3);
light_pin_mux(AOGPIO_11,0);
- light_pin_mux(AOGPIO_12,0);
- light_pin_mux(AOGPIO_13,0);
+ light_pin_mux(AOGPIO_12,0); ///aud-tx
+ light_pin_mux(AOGPIO_13,0); ///aud-rx
light_pin_mux(AOGPIO_14,0);
light_pin_mux(AOGPIO_15,0);
+
light_pin_mux(AUDIO_PA9,3);
- light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_mux(AUDIO_PA10,3);
+ light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2); ///audio-pa-rst
+ light_pin_mux(AUDIO_PA10,3); ///aud_3v3_en
light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_mux(AUDIO_PA12,3);
+ light_pin_mux(AUDIO_PA12,3); ///aud_1v8_en
light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA13,0);
/*ap-padmux on left/top */
light_pin_mux(QSPI1_CSN0,3);
- light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+ light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8); ///se-spi
+ light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8); ///se-spi
+ light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8); ///se-spi
+ light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8); ///se-spi
+ light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8); ///uart5-rx
+ light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8); ///uart5-tx
light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(GPIO0_30,0);
light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2); /// NC
+ light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2); /// AVDD25_IR_EN
+ light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2); /// DVDD12_IR_EN
+ light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PN,2); /// vdd-3v3-en (gmac,uart,led)
light_pin_mux(GPIO1_0,1);
light_pin_mux(GPIO1_1,1);
light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); ///VDD18_LCD0_EN
+ light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2); ///LCD0_BIAS_EN
+ light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2); /// LCD_ID0
+ light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2); /// VDD28_TP0_EN
+ light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2); /// DOVDD18_RGB_EN
+ light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2); /// DVDD12_RGB_EN
+ light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_PN,2); /// AVDD28_RGB_EN
+ light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2); /// RGBCAM_RESET
light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PD,2);
+ light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2); /// DBB2LEDDRIVER_EN1
light_pin_mux(CLK_OUT_0,1);
light_pin_mux(CLK_OUT_1,1);
light_pin_mux(CLK_OUT_3,1);
light_pin_mux(CLK_OUT_2,3);
- light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2); ///volume key
/*ap-pdmux on righ/top*/
light_pin_mux(QSPI0_SCLK,2);
light_pin_mux(SPI_MOSI,3);
light_pin_mux(SPI_MISO,3);
light_pin_mux(SPI_SCLK,3);
- light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
light_pin_mux(GPIO2_18,0);
light_pin_mux(GPIO2_19,0);
light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
+ light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_GPIO2
+ light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_GPIO3
+ light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2); ///WIFI_BT_RST_N
+ light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2); ///KEY1
light_pin_mux(SDIO0_WPRTN,3);
- light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
light_pin_mux(SDIO1_WPRTN,3);
- light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2); ///VBUS_EN
light_pin_mux(SDIO1_DETN,3);
- light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2); ///WCN33_EN
light_pin_mux(GPIO2_30,0);
light_pin_mux(GPIO2_31,0);
light_pin_mux(GPIO3_0,0);
+
light_pin_mux(GPIO3_1,0);
light_pin_mux(GPIO3_2,1);
light_pin_mux(GPIO3_3,0);
- light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PU, 0x2);
- light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2);
- light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PU, 0x2);
+ light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+ light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+ light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
- light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2);
+ light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2); /// WAKEUP_IN_CAT1
light_pin_mux(GMAC0_COL,3);
light_pin_mux(GMAC0_CRS,3);
light_pin_cfg(GMAC0_RXD2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GMAC0_RXD3, PIN_SPEED_NORMAL, PIN_PN, 0xF);
}
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
static void light_iopin_init(void)
{
/* aon-padmux config */
light_pin_cfg(I2C_AON_SCL,PIN_SPEED_NORMAL,PIN_PN,8);
light_pin_cfg(I2C_AON_SDA,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(AOGPIO_7,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
+ light_pin_cfg(AOGPIO_8,PIN_SPEED_NORMAL,PIN_PN,2); ///NC
light_pin_cfg(AOGPIO_9,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_10,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(AOGPIO_11,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_mux(AOGPIO_14,0);
light_pin_mux(AOGPIO_15,0);
- light_pin_mux(AUDIO_PA9,3);
- light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_mux(AUDIO_PA10,3);
+ light_pin_mux(AUDIO_PA9,3); ///AUDIO-PA-RESET
+ light_pin_cfg(AUDIO_PA9,PIN_SPEED_NORMAL,PIN_PN,2);
+ light_pin_mux(AUDIO_PA10,3); /// AUD-3V3-EN
light_pin_cfg(AUDIO_PA10,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_mux(AUDIO_PA12,3);
+ light_pin_mux(AUDIO_PA12,3); /// AUD-1V8-EN
light_pin_cfg(AUDIO_PA12,PIN_SPEED_NORMAL,PIN_PU,2);
light_pin_mux(AUDIO_PA13,0);
/*ap-padmux on left/top */
light_pin_mux(QSPI1_CSN0,3);
- light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8);
- light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PU,8);
- light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PU,8);
+ light_pin_cfg(QSPI1_CSN0,PIN_SPEED_NORMAL,PIN_PN,8); ///se-spi
+ light_pin_cfg(QSPI1_SCLK,PIN_SPEED_NORMAL,PIN_PN,8); ///se-spi
+ light_pin_cfg(QSPI1_D0_MOSI,PIN_SPEED_NORMAL,PIN_PU,8); ///se-spi
+ light_pin_cfg(QSPI1_D1_MISO,PIN_SPEED_NORMAL,PIN_PU,8); ///se-spi
+ light_pin_cfg(QSPI1_D2_WP,PIN_SPEED_NORMAL,PIN_PN,8); ///NC
+ light_pin_cfg(QSPI1_D3_HOLD,PIN_SPEED_NORMAL,PIN_PN,8); ///NC
light_pin_cfg(I2C0_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C0_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_mux(GPIO0_30,0);
light_pin_cfg(GPIO0_20,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO0_21,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PD,2); ///< NC(not used)
- light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PD,2); ///<AVDD25_IR_EN
- light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PD,2); ///<DVDD12_IR_EN
- light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(GPIO0_27,PIN_SPEED_NORMAL,PIN_PN,2); ///< NC(not used)
+ light_pin_cfg(GPIO0_28,PIN_SPEED_NORMAL,PIN_PN,2); ///< AVDD25_IR_EN
+ light_pin_cfg(GPIO0_29,PIN_SPEED_NORMAL,PIN_PN,2); ///< DVDD12_IR_EN
+ light_pin_cfg(GPIO0_30,PIN_SPEED_NORMAL,PIN_PU,2); ///< gmac,uart,led
light_pin_mux(GPIO1_0,1);
light_pin_mux(GPIO1_1,1);
light_pin_cfg(GPIO1_2,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_3,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_4,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PD,2); ///<VDD18_LCD0_EN
- light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PD,2); ///<LCD0_BIAS_EN
+ light_pin_cfg(GPIO1_9,PIN_SPEED_NORMAL,PIN_PN,2); ///<VDD18_LCD0_EN
+ light_pin_cfg(GPIO1_10,PIN_SPEED_NORMAL,PIN_PN,2); ///<LCD0_BIAS_EN
light_pin_cfg(GPIO1_11,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PD,2); ///<TOUCH-PANNEL VDD28_TP0_EN
- light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PD,2); ///<DOVDD18_RGB_EN
- light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PD,2); ///<DVDD12_RGB_EN
- light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_P
D,2); ///<AVDD28_RGB_EN
+ light_pin_cfg(GPIO1_12,PIN_SPEED_NORMAL,PIN_PN,2); ///<TOUCH-PANNEL VDD28_TP0_EN
+ light_pin_cfg(GPIO1_13,PIN_SPEED_NORMAL,PIN_PN,2); ///<DOVDD18_RGB_EN
+ light_pin_cfg(GPIO1_14,PIN_SPEED_NORMAL,PIN_PN,2); ///<DVDD12_RGB_EN
+ light_pin_cfg(GPIO1_15,PIN_SPEED_NORMAL,PIN_P
N,2); ///<AVDD28_RGB_EN
light_pin_cfg(GPIO1_16,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_21,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_22,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PD,2); ///<LED_PDN
+ light_pin_cfg(GPIO1_23,PIN_SPEED_NORMAL,PIN_PN,2); ///<LED_PDN
light_pin_cfg(GPIO1_24,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO1_25,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PD,2); ///<DBB2LEDDRIVER_EN
+ light_pin_cfg(GPIO1_26,PIN_SPEED_NORMAL,PIN_PN,2); ///<DBB2LEDDRIVER_EN
light_pin_mux(CLK_OUT_0,1);
light_pin_mux(CLK_OUT_1,1);
light_pin_mux(CLK_OUT_3,1);
light_pin_mux(CLK_OUT_2,3);
- light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(CLK_OUT_2,PIN_SPEED_NORMAL,PIN_PU,2); ///volume key "-"
/*ap-pdmux on righ/top*/
- light_pin_mux(QSPI0_SCLK,2);
- light_pin_mux(QSPI0_CSN0,2);
- light_pin_mux(QSPI0_CSN1,2);
- light_pin_mux(QSPI0_D0_MOSI,2);
- light_pin_mux(QSPI0_D1_MISO,2);
- light_pin_mux(QSPI0_D2_WP,2);
- light_pin_mux(QSPI0_D3_HOLD,2);
+ light_pin_mux(QSPI0_SCLK,3); ///NC
+ light_pin_mux(QSPI0_CSN0,3); ///NC
+ light_pin_mux(QSPI0_CSN1,3); ///NC
+ light_pin_mux(QSPI0_D0_MOSI,3); ///NC
+ light_pin_mux(QSPI0_D1_MISO,3); ///NC
+ light_pin_mux(QSPI0_D2_WP,3); ///NC
+ light_pin_mux(QSPI0_D3_HOLD,3); ///NC
light_pin_cfg(I2C2_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C2_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C3_SCL,PIN_SPEED_NORMAL,PIN_PN,4);
light_pin_cfg(I2C3_SDA,PIN_SPEED_NORMAL,PIN_PN,4);
- light_pin_mux(SPI_CSN,3);
- light_pin_mux(SPI_MOSI,3);
- light_pin_mux(SPI_MISO,3);
+ light_pin_mux(SPI_CSN,3); /// W_DISABLE_CATE1
+ light_pin_mux(SPI_MOSI,3); /// NC
+ light_pin_mux(SPI_MISO,3); /// RERST1_N_CAT1
light_pin_mux(SPI_SCLK,3);
- light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SPI_SCLK,PIN_SPEED_NORMAL,PIN_PN,2); /// NC
light_pin_mux(GPIO2_18,0);
light_pin_mux(GPIO2_19,0);
light_pin_cfg(GPIO2_18,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_19,PIN_SPEED_NORMAL,PIN_PN,2);
light_pin_cfg(GPIO2_20,PIN_SPEED_NORMAL,PIN_PN,2);
- light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PD,2); ///<NC(not-connected)
- light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PU,2);
- light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(GPIO2_21,PIN_SPEED_NORMAL,PIN_PN,2); ///<NC
+ light_pin_cfg(GPIO2_22,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_GPIO2
+ light_pin_cfg(GPIO2_23,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_GPIO3
+ light_pin_cfg(GPIO2_24,PIN_SPEED_NORMAL,PIN_PN,2); ///<WIFI_BT_RST_N
+ light_pin_cfg(GPIO2_25,PIN_SPEED_NORMAL,PIN_PU,2); ///KEY1
light_pin_mux(SDIO0_WPRTN,3);
- light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO0_WPRTN,PIN_SPEED_NORMAL,PIN_PN,2); ///< NC
light_pin_mux(SDIO1_WPRTN,3);
- light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO1_WPRTN,PIN_SPEED_NORMAL,PIN_PU,2); ///VBUS_EN
light_pin_mux(SDIO1_DETN,3);
- light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PU,2);
+ light_pin_cfg(SDIO1_DETN,PIN_SPEED_NORMAL,PIN_PN,2); ///WCN_33_EN
light_pin_mux(GPIO2_30,0);
light_pin_mux(GPIO2_31,0);
light_pin_mux(GPIO3_1,0);
light_pin_mux(GPIO3_2,1);
light_pin_mux(GPIO3_3,0);
- light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PU, 0x2);
- light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PU, 0x2);
- light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PU, 0x2);
+ light_pin_cfg(GPIO2_30, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+ light_pin_cfg(GPIO2_31, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
+ light_pin_cfg(GPIO3_0, PIN_SPEED_NORMAL, PIN_PN, 0x2); ///NC
light_pin_cfg(GPIO3_1, PIN_SPEED_NORMAL, PIN_PN, 0x2);
light_pin_cfg(GPIO3_2, PIN_SPEED_NORMAL, PIN_PN, 0xF);
light_pin_cfg(GPIO3_3, PIN_SPEED_NORMAL, PIN_PN, 0x2);
static void light_usb_boot_check(void)
{
int boot_mode;
-
+ uchar env_enetaddr[6]={0};
+ uchar env_enet1addr[6]={0};
+ int env_ethaddr_flag,env_eth1addr_flag;
boot_mode = readl((void *)SOC_OM_ADDRBASE) & 0x7;
if (boot_mode & BIT(2))
return;
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("usb_fastboot", "yes");
#endif
+ /*Get this version ethaddr(mac addr) env,which follows one board, trans to next version env*/
+ env_ethaddr_flag = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr);
+ env_eth1addr_flag = eth_env_get_enetaddr_by_index("eth", 1, env_enet1addr);
run_command("env default -a -f", 0);
+ /*If mac addr in last version env is valid, before save,inherit env mac addr */
+ if(env_ethaddr_flag){
+ eth_env_set_enetaddr_by_index("eth", 0, env_enetaddr);
+ run_command("printenv ethaddr",0);
+ }else{
+ printf("env ethaddr not exist or invalid\n");
+ }
+
+ if(env_eth1addr_flag){
+ eth_env_set_enetaddr_by_index("eth", 1, env_enet1addr);
+ run_command("printenv eth1addr",0);
+ }else{
+ printf("env eth1addr not exist or invalid\n");
+ }
+
run_command("env save", 0);
run_command("run gpt_partition", 0);
run_command("fastboot usb 0", 0);
ap_peri_clk_disable();
return 0;
}
+
+static int do_env_ethaddr_check(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ uchar env_enetaddr[6]={0};
+ int i;
+ for(i=0;i<2;i++){
+ if(eth_env_get_enetaddr_by_index("eth", i, env_enetaddr)){
+ printf("env (eth%d) MAC address ok- %pM\n",i, env_enetaddr);
+ }
+ else {
+ printf("env (eth%d) MAC address invalid - %pM\n",i, env_enetaddr);
+ printf(" * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00,\n"
+ " is not a multicast address(first byte low bit zero is not multi addr), \n"
+ "and is not FF:FF:FF:FF:FF:FF.\n");
+ }
+
+ }
+ return 0;
+
+}
+
+U_BOOT_CMD(
+ chk_ethaddr, 2, 0, do_env_ethaddr_check,
+ "check ethaddrs in environment variables is valid",
+ ""
+);
REGU_ID_DEF(IIC_IDX_AONIIC,APCPU_REGU_VDDM,0x31,0x39,0,1,800000,600000,3500000,12500,1),
},
};
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
/**
- * board for ant-evt
+ * board for ant-ref
*
*/
static const struct regulator_t g_regu_id_list[] = {
int pmic_ddr_set_voltage(void)
{
- int ret = -1;
+ int ret = 0;
uint32_t val = 0;
uint32_t regu_num = ARRAY_SIZE(g_regu_id_list);
uint32_t i;
struct regulator_t *pregu;
csi_iic_t *dev_handle;
+#if 0 //currently,no need to modify ddr regulator voltage
pregu = (struct regulator_t*)g_regu_id_list;
for (i = 0; i < regu_num; i++, pregu++) {
if (pregu->regu_vol_target < pregu->regu_vol_min || pregu->regu_vol_target > pregu->regu_vol_max)
if (ret)
return ret;
}
+#endif
+
#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
/*enable lcd0_en ldo*/
pregu = (struct regulator_t*)&g_regu_id_list[LCD0_EN];
return ret;
return 0;
}
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)|| (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
int pmic_reset_apcpu_voltage(void)
{
int ret = -1;
return CMD_RET_FAILURE;
}
-U_BOOT_CMD(
- efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
- "eFuse sub-system",
- "read <addr> [<cnt>] - read 1 or 'cnt' fuse bytes,\n"
- " starting at 'addr'\n"
- "efuse write [-y] <addr> <hexval> [<hexval>...] - program 1 or\n"
- " several fuse bytes, starting at 'addr'\n"
-);
-
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
/* Secure function for image verificaiton here */
int get_image_version(unsigned long img_src_addr)
{
int verify_customer_image(img_type_t type, long addr)
{
int ret;
-
+ const char *image_name = "";
+
/* Double check image number */
if (image_have_head(addr) == 0)
return -1;
dump_image_header_info(addr);
/* Call customer image verification function */
- if ((type == T_TF) || (type == T_TEE)) {
+ if ((type == T_TF) || (type == T_TEE) || (type == T_KRLIMG)) {
ret = csi_sec_custom_image_verify(addr, UBOOT_STAGE_ADDR);
if (ret) {
- printf("Image(%s) is verified fail, Please go to check!\n\n", (type == T_TF)?"tf":"tee");
+ printf("Image(%d) is verified fail, Please go to check!\n\n", type);
return ret;
}
} else if (type == T_UBOOT) {
return 0;
}
-
+#else
+U_BOOT_CMD(
+ efuse, CONFIG_SYS_MAXARGS, 0, do_fuse,
+ "eFuse sub-system",
+ "read <addr> [<cnt>] - read 1 or 'cnt' fuse bytes,\n"
+ " starting at 'addr'\n"
+ "efuse write [-y] <addr> <hexval> [<hexval>...] - program 1 or\n"
+ " several fuse bytes, starting at 'addr'\n"
+);
#endif
csr_write(CSR_MHINT2_E, csr_read(CSR_MHINT2_E) | 0x20000);
csr_write(CSR_MHINT4, csr_read(CSR_MHINT4) | 0x410);
csr_write(CSR_MCCR2, 0xe2490009);
- csr_write(CSR_MHCR, 0x11ff);
+ csr_write(CSR_MHCR, 0x117f); // clear bit7 to disable indirect brantch prediction
csr_write(CSR_MXSTATUS, 0x638000);
- csr_write(CSR_MHINT, 0x6e30c);
+ csr_write(CSR_MHINT, 0x6e30c | (1<<22)); // set bit22 to close fence broadcast
}
static int bl1_img_have_head(unsigned long img_src_addr)
#define LIGHT_DSP_SUBSYS_ADDRBASE 0xffff041000
#define LIGHT_AUDIO_SUBSYS_ADDRBASE 0xffcb000000
#define LIGHT_APSYS_RSTGEN_ADDRBASE 0xffff015000
+#define LIGHT_DPU_CLOCK_GATING_CTRL0 0xffef601A28
+#define LIGHT_DPU_CLOCK_GATING_CTRL1 0xffef601A2C
void show_sys_clk(void)
{
tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
tmp |= 0x30;
writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+ /* The boards other than the LightA board perform the bus down-speed operation */
+
+#if defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE) || defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF) || defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER) || defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
+ /* axi_sram_clk: 812.8512MHz -> 688.128MHz */
+ tmp = readl((void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+ tmp |= 0x2000;
+ writel(tmp, (void *)LIGHT_AONCLK_ADDRBASE + 0x104);
+
+ /* visys_aclk_m decrease frequency 792MHZ->594MHZ */
+ tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+ tmp &= ~0x00100000;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+
+ tmp &= ~0x000f0000;
+ tmp |= 0x00140000;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1d0);
+ /* vosys_aclk_m：792MHz->594MHz */
+ tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+ tmp &= ~0x00000020;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+ tmp &= ~0x0000000f;
+ tmp |= 0x00000024;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1dc);
+
+ /* vpsys_axi_aclk：792MHz->594MHz */
+ tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+ tmp &= ~0x00001000;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+ tmp &= ~0x00000f00;
+ tmp |= 0x00001400;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1e0);
+
+ /* npu_cclk：1000MHz->792MHz */
+ tmp = readl((void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+ tmp |= 0x00000040;
+ writel(tmp, (void *)LIGHT_APCLK_ADDRBASE + 0x1c8);
+
+
+ /* Enable dpu auto clock gating */
+ writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL0);
+ writel(0, (void __iomem *)LIGHT_DPU_CLOCK_GATING_CTRL1);
+#endif
+
#endif
}
--- /dev/null
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <thead/clock_config.h>
+#include <linux/bitops.h>
+#include <asm/arch-thead/light-iopmp.h>
+#include <asm/arch-thead/light-plic.h>
+
+#define DW_TIMER0_BASE 0xffefc32000
+#define DW_TIMER0_TLC_REG (DW_TIMER0_BASE + 0x00) /* Offset: 0x000 (R/W) TimerLoadCount */
+#define DW_TIMER0_TCV_REG (DW_TIMER0_BASE + 0X04) /* Offset: 0x004 (R/ ) TimerCurrentValue */
+#define DW_TIMER0_TCR_REG (DW_TIMER0_BASE + 0X08) /* Offset: 0x008 (R/W) TimerControlReg */
+#define DW_TIMER0_TEOI_REG (DW_TIMER0_BASE + 0X0C) /* Offset: 0x00c (R/ ) TimerEOI */
+#define DW_TIMER0_TIS_REG (DW_TIMER0_BASE + 0X10) /* Offset: 0x010 (R/ ) TimerIntStatus */
+
+/*! Timer Int Status, offset: 0x10 */
+#define DW_TIMER_INT_STATUS_Pos (0U)
+#define DW_TIMER_INT_STATUS_Msk (0x1U << DW_TIMER_INT_STATUS_Pos)
+#define DW_TIMER_INT_STATUS_EN DW_TIMER_INT_STATUS_Msk
+
+/*! Timer1 Control Reg, offset: 0x08 */
+#define DW_TIMER_CTL_ENABLE_SEL_Pos (0U)
+#define DW_TIMER_CTL_ENABLE_SEL_Msk (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
+#define DW_TIMER_CTL_ENABLE_SEL_EN DW_TIMER_CTL_ENABLE_SEL_Msk
+
+#define DW_TIMER_CTL_MODE_SEL_Pos (1U)
+#define DW_TIMER_CTL_MODE_SEL_Msk (0x1U << DW_TIMER_CTL_MODE_SEL_Pos)
+#define DW_TIMER_CTL_MODE_SEL_EN DW_TIMER_CTL_MODE_SEL_Msk
+
+#define DW_TIMER_CTL_INT_MASK_Pos (2U)
+#define DW_TIMER_CTL_INT_MASK_Msk (0x1U << DW_TIMER_CTL_INT_MASK_Pos)
+#define DW_TIMER_CTL_INT_MAKS_EN DW_TIMER_CTL_INT_MASK_Msk
+
+#define DW_TIMER_CTL_HARD_TRIG_Pos (4U)
+#define DW_TIMER_CTL_HARD_TRIG_Msk (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos)
+#define DW_TIMER_CTL_HARD_TRIG_EN DW_TIMER_CTL_HARD_TRIG_Msk
+
+/*! Timer EOI, offset: 0x0c */
+#define DW_TIMER_EOI_REG_Pos (0U)
+#define DW_TIMER_EOI_REG_Msk (0x1U << DW_TIMER_EOI_REG_Pos)
+#define DW_TIMER_EOI_REG_EN DW_TIMER_EOI_REG_Msk
+
+#define TIMER0_IRQ_NUM 16
+#define TIMER0_FREQ_HZ 125000000U
+#define DW_TIMER_GET_RELOAD_VAL(_tim_, _frq_) ((_tim_ < 25000U) ? ((_frq_ * _tim_) / 1000U) : (_frq_ * (_tim_ / 1000U)))
+
+static int time_user_defined_flag = 0;
+
+static void csi_timer_stop(void);
+
+static inline u32 dw_timer_get_int_status(void)
+{
+ return (readl((void __iomem *)DW_TIMER0_TIS_REG) & DW_TIMER_INT_STATUS_EN) ? 1 : 0;
+}
+
+static inline void dw_timer_clear_irq(void)
+{
+ readl((void __iomem *)DW_TIMER0_TEOI_REG);
+}
+
+static inline void dw_timer_write_load(uint32_t value)
+{
+ writel(value, (void __iomem *)DW_TIMER0_TLC_REG);
+}
+
+static inline void dw_timer_set_mode_load(void)
+{
+ writel((readl((void __iomem *)DW_TIMER0_TCR_REG) | DW_TIMER_CTL_MODE_SEL_EN), (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_disable(void)
+{
+ u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+ data &= ~DW_TIMER_CTL_ENABLE_SEL_EN;
+ writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_enable(void)
+{
+ u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+ data |= DW_TIMER_CTL_ENABLE_SEL_EN;
+ writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_unmask(void)
+{
+ u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+ data &= ~DW_TIMER_CTL_INT_MAKS_EN;
+ writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static inline void dw_timer_set_mask(void)
+{
+ u32 data = readl((void __iomem *)DW_TIMER0_TCR_REG);
+
+ data |= DW_TIMER_CTL_INT_MAKS_EN;
+ writel(data, (void __iomem *)DW_TIMER0_TCR_REG);
+}
+
+static void dw_timer_irq_handler(void)
+{
+ debug("[%s,%d]\n", __func__, __LINE__);
+ if (dw_timer_get_int_status()) {
+ dw_timer_clear_irq();
+ csi_timer_stop();
+ debug("[%s,%d]\n", __func__, __LINE__);
+ time_user_defined_flag = 1;
+ }
+}
+
+static inline void dw_timer_reset_register(void)
+{
+ writel(0, (void __iomem *)DW_TIMER0_TLC_REG);
+ writel(0, (void __iomem *)DW_TIMER0_TCV_REG);
+}
+
+static int csi_timer_start(u32 timeout_us)
+{
+ u32 timer_freq = TIMER0_FREQ_HZ;
+ u32 tmp_load = DW_TIMER_GET_RELOAD_VAL(timeout_us, timer_freq);
+
+ dw_timer_set_mode_load();
+
+ //FIXME: no less than 10
+ if (tmp_load < 10)
+ tmp_load = 10;
+
+ dw_timer_write_load(tmp_load);
+
+ dw_timer_set_disable();
+ dw_timer_set_enable();
+ dw_timer_set_unmask();
+
+ return 0;
+}
+
+static void csi_timer_stop(void)
+{
+ dw_timer_set_mask();
+ dw_timer_set_disable();
+}
+
+static void timer_interrupt_init(void)
+{
+ irq_handler_register(TIMER0_IRQ_NUM, dw_timer_irq_handler);
+ irq_priority_set(TIMER0_IRQ_NUM);
+ irq_enable(TIMER0_IRQ_NUM);
+ arch_local_irq_enable();
+}
+
+static void timer_interrupt_uninit(void)
+{
+ arch_local_irq_disable();
+ irq_disable(TIMER0_IRQ_NUM);
+}
+
+static int csi_timer_init(void)
+{
+ dw_timer_reset_register();
+ timer_interrupt_init();
+ return 0;
+}
+
+static void csi_timer_uinit(void)
+{
+ timer_interrupt_uninit();
+ dw_timer_reset_register();
+}
+
+int timer_alarm_set(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned long time_us;
+ int ret, state;
+ u32 timeout = 0;
+
+ if (argc != 2) {
+ printf("invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (strict_strtoul(argv[1], 10, &time_us) < 0)
+ return CMD_RET_USAGE;
+
+ time_us = time_us * 1000000;
+ ret = csi_timer_init();
+ if(ret) {
+ printf("failed to initialize the timer\n");
+ return -EINVAL;
+ }
+
+ time_user_defined_flag = 0;
+ state = csi_timer_start(time_us);
+ if (state) {
+ printf("failed to start the timer0\n");
+ return ret;
+ }
+
+ do {
+
+ timeout++;
+ //if (!timeout)
+ // break;
+ mdelay(1000);
+ printf("[%s,%d]wait for timer interrupt, %d seconds elapsed\n",
+ __func__, __LINE__, timeout);
+
+ } while (!time_user_defined_flag);
+
+ csi_timer_uinit();
+
+ return 0;
+}
+
+U_BOOT_CMD(timer_alarm, 2, 0, timer_alarm_set, "timer_alarm 10", "timer interrupt test");
--- /dev/null
+/*
+ * Copyright (C) 2017-2020 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <env.h>
+
+
+static int rollback_part(const char *partition, const char *partition_alt)
+{
+ char *p;
+ int ret;
+ int tmp;
+
+ p = env_get(partition_alt);
+ if (p == NULL) {
+ return 0;
+ }
+ tmp = 1;
+ printf("Rollback partition %s to %s\n", partition, p);
+ ret = env_set(partition, p);
+ if (ret) {
+ printf("Failed to set env %s %s: ret = %d\n", partition, p, ret);
+ tmp = -1;
+ }
+ ret = env_set(partition_alt, NULL);
+ if (ret) {
+ printf("Failed to del env %s: ret = %d\n", partition_alt, ret);
+ tmp = -1;
+ }
+ return tmp;
+}
+
+static int upgrade_rollback_check(void)
+{
+ unsigned long bootlimit;
+ unsigned long bootcount;
+ char *p;
+ char buf[20];
+ int ret;
+ int save;
+
+ p = env_get("bootlimit");
+ if (p == NULL) {
+ return -1;
+ }
+ if (!strcmp(p, "0")) {
+ return 0;
+ } else {
+ if (strict_strtoul(p, 16, &bootlimit) < 0) {
+ printf("Failed to strict_strtoul bootlimit\n");
+ return -1;
+ }
+ }
+ p = env_get("bootcount");
+ if (p == NULL) {
+ bootcount = 0;
+ } else if (strict_strtoul(p, 16, &bootcount) < 0) {
+ bootcount = 0;
+ }
+ save = 0;
+ bootcount++;
+ if (bootcount == bootlimit + 1) {
+ save = 1;
+ printf("Failed to start for %lu times, will rollback!\n", bootlimit);
+ rollback_part("boot_partition", "boot_partition_alt");
+ rollback_part("root_partition", "root_partition_alt");
+ } else if (bootcount < bootlimit + 1) {
+ save = 1;
+ }
+ if (save) {
+ snprintf(buf, sizeof(buf), "%lu", bootcount);
+ ret = env_set("bootcount", buf);
+ if (ret) {
+ printf("Failed to set env bootcount %s: ret = %d\n", buf, ret);
+ }
+ ret = env_save();
+ if (ret) {
+ printf("Failed to env_save: ret = %d\n", ret);
+ }
+ }
+
+ return 0;
+}
+
+static int do_rollback(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ upgrade_rollback_check();
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ rollback, 1, 1, do_rollback,
+ "Automatic rollback if upgrade fails",
+ NULL
+);
#endif
-#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#if CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B) || CONFIG_IS_ENABLED(LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
extern int light_secboot(int argc, char * const argv[]);
int do_secboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- if (light_secboot(argc, argv) != 0)
- return -1;
+ if (light_secboot(argc, argv) != 0) {
+ run_command("reset", 0);
+ return -1;
+ }
return 0;
}
PLATFORM_CPPFLAGS += -finstrument-functions -DFTRACE
endif
+ifeq ($(BUILD_TYPE),RELEASE)
+PLATFORM_CPPFLAGS += -DU_BUILD_RELEASE
+else # default build debug
+PLATFORM_CPPFLAGS += -DU_BUILD_DEBUG
+endif
#########################################################################
RELFLAGS := $(PLATFORM_RELFLAGS)
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_A_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
CONFIG_SPL=y
CONFIG_SMP=y
CONFIG_TARGET_LIGHT_C910=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
# CONFIG_ISO_PARTITION is not set
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
+++ /dev/null
-CONFIG_RISCV=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xe0000
-CONFIG_NR_DRAM_BANKS=8
-CONFIG_SPL=y
-CONFIG_SMP=y
-CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
-CONFIG_DISPLAY_CPUINFO=y
-CONFIG_DISPLAY_BOARDINFO=y
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
-CONFIG_DDR_LP4X_3200_SINGLERANK=y
-CONFIG_DDR_H32_MODE=y
-# CONFIG_DDR_LP4_3733_DUALRANK is not set
-CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_CMD_BOOT_SLAVE=y
-CONFIG_CMD_ERASEENV=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_DDR_SCAN=y
-CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_CLK=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_UDP_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DWAPB_GPIO=y
-# CONFIG_MMC_SPI is not set
-CONFIG_MMC_VERBOSE=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_SNPS=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SNPS=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MMC_RPMB=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_PHY_REALTEK=y
-CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
-CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_DESIGNWARE_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1234
-CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-# CONFIG_EFI_LOADER is not set
-# CONFIG_LIGHT_SEC_BOOT is not set
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_VIDEO=y
-CONFIG_PHY=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CMD_BMP=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_DM_PCA953X=y
-CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
-CONFIG_VIDEO_DW_DSI_LIGHT=y
-CONFIG_VIDEO_DW_DPHY=y
-CONFIG_VIDEO_DW_DSI_HOST=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SYS_TEXT_BASE=0x7b000000
-CONFIG_PMIC_VOL_INIT=y
-CONFIG_DDR_REGU_0V6=600000
-CONFIG_DDR_REGU_0V8=800000
-CONFIG_DDR_REGU_1V1=1100000
+++ /dev/null
-CONFIG_RISCV=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0xe0000
-CONFIG_NR_DRAM_BANKS=8
-CONFIG_SPL=y
-CONFIG_SMP=y
-CONFIG_TARGET_LIGHT_C910=y
-CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
-CONFIG_DISPLAY_CPUINFO=y
-CONFIG_DISPLAY_BOARDINFO=y
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SYS_PROMPT="C910 Light# "
-CONFIG_DDR_LP4X_3200_SINGLERANK=y
-CONFIG_DDR_H32_MODE=y
-# CONFIG_DDR_LP4_3733_DUALRANK is not set
-CONFIG_DDR_BOARD_CONFIG=y
-CONFIG_CMD_BOOT_SLAVE=y
-CONFIG_CMD_ERASEENV=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_DDR_SCAN=y
-CONFIG_DDR_PRBS_TEST=n
-# CONFIG_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_PARTITION_TYPE_GUID=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="light-ant-evt"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_CLK=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_UDP_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x10000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_DW=y
-CONFIG_DWAPB_GPIO=y
-# CONFIG_MMC_SPI is not set
-CONFIG_MMC_VERBOSE=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_SNPS=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SNPS=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_MMC_RPMB=y
-CONFIG_SUPPORT_EMMC_RPMB=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_PHY_REALTEK=y
-CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
-CONFIG_RTL8211X_PHY_FORCE_MASTER=y
-CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DESIGNWARE_SPI=y
-CONFIG_DESIGNWARE_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1234
-CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
-# CONFIG_SPL_USE_TINY_PRINTF is not set
-# CONFIG_EFI_LOADER is not set
-CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT=y
-CONFIG_LIGHT_SEC_UPGRADE=y
-CONFIG_BOARD_LATE_INIT=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_VIDEO=y
-CONFIG_PHY=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_CMD_BMP=y
-CONFIG_VIDEO_BRIDGE=y
-CONFIG_DM_PCA953X=y
-CONFIG_VIDEO_VS_DPU=y
-CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
-CONFIG_VIDEO_DW_DSI_LIGHT=y
-CONFIG_VIDEO_DW_DPHY=y
-CONFIG_VIDEO_DW_DSI_HOST=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_SYS_TEXT_BASE=0x7b000000
-CONFIG_PMIC_VOL_INIT=y
-CONFIG_DDR_REGU_0V6=600000
-CONFIG_DDR_REGU_0V8=800000
-CONFIG_DDR_REGU_1V1=1100000
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-ant-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF=y
+CONFIG_LIGHT_SEC_UPGRADE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_B_POWER=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-power"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_B_REF=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3200_SINGLERANK=y
+CONFIG_DDR_H32_MODE=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_TIME=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-b-ref"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SYS_TEXT_BASE=0x7b000000
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0xe0000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SPL=y
+CONFIG_SMP=y
+CONFIG_TARGET_LIGHT_C910=y
+CONFIG_TARGET_LIGHT_FM_C910_BEAGLE=y
+# CONFIG_THEAD_PLIC is not set
+# CONFIG_THEAD_LIGHT_TIMER is not set
+# CONFIG_THEAD_LIGHT_DIGITAL_SENSOR is not set
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_PROMPT="C910 Light# "
+CONFIG_DDR_LP4X_3733_SINGLERANK=y
+# CONFIG_DDR_LP4_3733_DUALRANK is not set
+CONFIG_DDR_BOARD_CONFIG=y
+CONFIG_CMD_BOOT_SLAVE=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_DDR_SCAN=y
+CONFIG_DDR_PRBS_TEST=n
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="light-a-val"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DWAPB_GPIO=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_VERBOSE=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SNPS=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_REALTEK=y
+CONFIG_RTL8211E_PINE64_GIGABIT_FIX=y
+CONFIG_RTL8211X_PHY_FORCE_MASTER=y
+CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DESIGNWARE_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="U-Boot-THEAD"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1234
+CONFIG_USB_GADGET_PRODUCT_NUM=0x8888
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LIGHT_SEC_BOOT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_VIDEO=y
+CONFIG_PHY=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_DM_PCA953X=y
+CONFIG_VIDEO_VS_DPU=y
+CONFIG_VIDEO_LCD_ILITEK_ILI9881C=y
+CONFIG_VIDEO_DW_DSI_LIGHT=y
+CONFIG_VIDEO_DW_DPHY=y
+CONFIG_VIDEO_DW_DSI_HOST=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_PMIC_VOL_INIT=y
+CONFIG_DDR_REGU_0V6=600000
+CONFIG_DDR_REGU_0V8=800000
+CONFIG_DDR_REGU_1V1=1100000
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
static void oem_format(char *, char *);
#endif
+static void oem_command(char *, char *);
static const struct {
const char *command;
.dispatch = oem_format,
},
#endif
+ [FASTBOOT_COMMAND_OEM_COMMAND] = {
+ .command = "oem command",
+ .dispatch = oem_command,
+ },
};
/**
}
}
#endif
+
+/**
+ * oem_command() - Execute the OEM command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void oem_command(char *cmd_parameter, char *response)
+{
+ if (run_command(cmd_parameter, 0))
+ fastboot_fail("", response);
+ else
+ fastboot_okay(NULL, response);
+}
dep->flags &= ~DWC3_EP_BUSY;
dep->resource_index = 0;
dwc->setup_packet_pending = false;
+ invalid_dcache_range(dwc->ctrl_req, (dmaaddr_t)dwc->ctrl_req + ROUND(sizeof(*dwc->ctrl_req), CACHELINE_SIZE));
switch (dwc->ep0state) {
case EP0_SETUP_PHASE:
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_SDRAM_BASE 0
#define MEMTEST_MAX_SIZE 0x200000000 /* 8GB DDR */
#define CONFIG_SYS_MEMTEST_START 0x00000000 // larger than Uboot end addr
#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_BASE + MEMTEST_MAX_SIZE
#define TEE_PART_NAME "tee"
#define UBOOT_PART_NAME "uboot"
#define STASH_PART_NAME "stash"
+#define KERNEL_PART_NAME "kernel"
#define UBOOT_STAGE_ADDR SRAM_BASE_ADDR
#define UBOOT_SEC_UPGRADE_FLAG 0xa5a5aa55
#define UBOOT_MAX_VER 64
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
+/* List of different env in debug/release version */
+#if defined (U_BUILD_DEBUG)
+#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=7\0"
+#define ENV_STR_BOOT_DELAY
+#else
+#define ENV_KERNEL_LOGLEVEL "kernel_loglevel=4\0"
+#define ENV_STR_BOOT_DELAY "bootdelay=0\0"
+#endif
#if defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_A)
#define CONFIG_EXTRA_ENV_SETTINGS \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
+ "kdump_buf=1M\0" \
"uboot_version=0x0000000000000000\0"\
"fdt_file=light-a-val-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_VAL_B)
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
+ "kdump_buf=1M\0" \
"uboot_version=0x0000000000000000\0"\
"fdt_file=light-b-product-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
-#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_EVT)
+#elif defined (CONFIG_LIGHT_SEC_BOOT_WITH_VERIFY_ANT_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"tf_addr=0x100000\0" \
"sec_upgrade_mode=0\0"\
"mmcdev=0\0" \
"mmcpart=6\0" \
+ "kdump_buf=1M\0" \
"uboot_version=0x0000000000000000\0"\
- "fdt_file=light-ant-evt-sec.dtb\0" \
+ "fdt_file=light-ant-ref-sec.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=tf,size=50MiB,type=boot;name=tee,size=50MiB,type=boot;name=stash,size=50MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:3 $tf_addr trust_firmware.bin; ext4load mmc 0:4 $tee_addr tee.bin;ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; secboot; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
#else
"fwaddr=0x10000000\0"\
"mmcdev=0\0" \
"mmcpart=3\0" \
+ "kdump_buf=1M\0" \
"fdt_file=light-a-product.dtb\0" \
"uuid_rootfs=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfs};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc 0:2 $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc 0:2 $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run load_aon;run load_c906_audio; ext4load mmc 0:2 $opensbi_addr fw_dynamic.bin; ext4load mmc 0:2 $dtb_addr ${fdt_file}; ext4load mmc 0:2 $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_B)
#define CONFIG_EXTRA_ENV_SETTINGS \
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
- "findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ ENV_KERNEL_LOGLEVEL \
+ "kdump_buf=1M\0" \
+ ENV_STR_BOOT_DELAY \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-b-product.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=${kernel_loglevel} eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
"bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
-#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_EVT)
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_REF)
#define CONFIG_EXTRA_ENV_SETTINGS \
"splashimage=0x30000000\0" \
"splashpos=m,m\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
"findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
- "fdt_file=light-ant-evt.dtb\0" \
+ "fdt_file=light-b-ref.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+ "bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file};ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image;\0" \
+ "bootcmd=run bootcmd_load; bootslave ; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_B_POWER)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "splashimage=0x30000000\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "opensbi_addr=0x0\0" \
+ "dtb_addr=0x01f00000\0" \
+ "kernel_addr=0x00200000\0" \
+ "aon_ram_addr=0xffffef8000\0" \
+ "audio_ram_addr=0xffc0000000\0" \
+ "fwaddr=0x10000000\0"\
+ "mmcdev=0\0" \
+ "boot_partition=bootA\0" \
+ "root_partition=rootfsA\0" \
+ "kdump_buf=1M\0" \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "fdt_file=light-b-power.dtb\0" \
+ "uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+ "uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+ "partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+ "gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+ "load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+ "load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+ "bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+ "bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
+ "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_REF)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "splashimage=0x30000000\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "opensbi_addr=0x0\0" \
+ "dtb_addr=0x01f00000\0" \
+ "kernel_addr=0x00200000\0" \
+ "aon_ram_addr=0xffffef8000\0" \
+ "audio_ram_addr=0xffc0000000\0" \
+ "fwaddr=0x10000000\0"\
+ "mmcdev=0\0" \
+ "boot_partition=bootA\0" \
+ "root_partition=rootfsA\0" \
+ "kdump_buf=1M\0" \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "fdt_file=light-ant-ref.dtb\0" \
+ "uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+ "uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+ "partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+ "gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+ "load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+ "load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
#elif defined (CONFIG_TARGET_LIGHT_FM_C910_VAL_ANT_DISCRETE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
- "findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "kdump_buf=1M\0" \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-ant-discrete.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+ "load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+ "load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+ "bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+ "bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
+ "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_BEAGLE)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "splashimage=0x30000000\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "opensbi_addr=0x0\0" \
+ "dtb_addr=0x01f00000\0" \
+ "kernel_addr=0x00200000\0" \
+ "aon_ram_addr=0xffffef8000\0" \
+ "audio_ram_addr=0xffc0000000\0" \
+ "fwaddr=0x10000000\0"\
+ "mmcdev=0\0" \
+ "boot_partition=bootA\0" \
+ "root_partition=rootfsA\0" \
+ "kdump_buf=500M\0" \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "fdt_file=light-beagle.dtb\0" \
+ "uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+ "uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+ "partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+ "gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
+ "load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
+ "load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
+ "bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
+ "bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
+ "\0"
+#elif defined (CONFIG_TARGET_LIGHT_FM_C910_A_REF)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "splashimage=0x30000000\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "opensbi_addr=0x0\0" \
+ "dtb_addr=0x01f00000\0" \
+ "kernel_addr=0x00200000\0" \
+ "aon_ram_addr=0xffffef8000\0" \
+ "audio_ram_addr=0xffc0000000\0" \
+ "fwaddr=0x10000000\0"\
+ "mmcdev=0\0" \
+ "boot_partition=bootA\0" \
+ "root_partition=rootfsA\0" \
+ "findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "fdt_file=light-a-ref.dtb\0" \
+ "uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
+ "uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
+ "partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
+ "finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
+ "gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
"set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"mmcdev=0\0" \
"boot_partition=bootA\0" \
"root_partition=rootfsA\0" \
- "findpart=if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
+ "kdump_buf=500M\0" \
+ "findpart=rollback; if test ${boot_partition} = bootB; then mmcbootpart=4; else mmcbootpart=2; fi; if test ${root_partition} = rootfsB; then mmcpart=5; else mmcpart=3; fi;\0" \
"fdt_file=light-a-val.dtb\0" \
"uuid_rootfsA=80a5a8e9-c744-491a-93c1-4f4194fd690a\0" \
"uuid_rootfsB=80a5a8e9-c744-491a-93c1-4f4194fd690b\0" \
"partitions=name=table,size=2031KB;name=boot,size=200MiB,type=boot;name=root,size=4000MiB,type=linux,uuid=${uuid_rootfsA};name=bootB,size=200MiB,type=boot;name=rootB,size=4000MiB,type=linux,uuid=${uuid_rootfsB};name=data,size=-,type=linux\0" \
"finduuid=part uuid mmc ${mmcdev}:${mmcpart} uuid\0" \
"gpt_partition=gpt write mmc ${mmcdev} $partitions\0" \
- "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime\0" \
+ "set_bootargs=setenv bootargs console=ttyS0,115200 root=PARTUUID=${uuid} rootfstype=ext4 rdinit=/sbin/init rootwait rw earlycon clk_ignore_unused loglevel=7 eth=$ethaddr rootrw=PARTLABEL=data init=/init rootinit=/sbin/init rootrwoptions=rw,noatime rootrwreset=${factory_reset} crashkernel=${kdump_buf}\0" \
"load_aon=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_aon_fpga.bin;cp.b $fwaddr $aon_ram_addr $filesize\0"\
"load_c906_audio=ext4load mmc ${mmcdev}:${mmcbootpart} $fwaddr light_c906_audio.bin;cp.b $fwaddr $audio_ram_addr $filesize\0"\
"bootcmd_load=run findpart;run load_aon;run load_c906_audio; ext4load mmc ${mmcdev}:${mmcbootpart} $opensbi_addr fw_dynamic.bin; ext4load mmc ${mmcdev}:${mmcbootpart} $dtb_addr ${fdt_file}; ext4load mmc ${mmcdev}:${mmcbootpart} $kernel_addr Image\0" \
"bootcmd=run bootcmd_load; bootslave; run finduuid; run set_bootargs; booti $kernel_addr - $dtb_addr;\0" \
+ "factory_reset=yes\0"\
"\0"
#endif
#endif
FASTBOOT_COMMAND_ACMD,
FASTBOOT_COMMAND_UCMD,
#endif
+ FASTBOOT_COMMAND_OEM_COMMAND,
FASTBOOT_COMMAND_COUNT
};
LIGHT_DPU1_PLL,
};
+struct clk_info {
+ const char *clk_name;
+ enum clk_device_type clk_dev_type;
+};
+
int clk_config(void);
int clk_light_set_rate(const char *clk_name, enum clk_device_type clk_dev_type, unsigned long rate);
unsigned long clk_light_get_rate(const char *clk_name, enum clk_device_type clk_dev_type);
+int clk_light_set_parent(const char *clk_name, const char *parent);
+const struct clk_info *clk_light_get_parent(const char *clk_name);
void ap_dpu_clk_endisable(bool en);
void ap_hdmi_clk_endisable(bool en);
/* Override the ROM MAC address */
memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN);
+ printf("%s (eth%d) using MAC address - %pM\n",
+ dev->name, dev->seq, pdata->enetaddr);
} else if (is_valid_ethaddr(pdata->enetaddr)) {
eth_env_set_enetaddr_by_index("eth", dev->seq, pdata->enetaddr);
printf("\nWarning: %s using MAC address from ROM\n",
projects / platform / kernel / u-boot-thead.git / commitdiff