STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
- bool shared_consts_enable = builder->layout->push_constant_size > 0;
+ bool shared_consts_enable = tu6_shared_constants_enable(builder->layout,
+ builder->device->compiler);
tu6_emit_shared_consts_enable(cs, shared_consts_enable);
tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
stage_infos[stage] = &builder->create_info->pStages[i];
}
- if (builder->layout->push_constant_size > 0) {
+ if (tu6_shared_constants_enable(builder->layout, builder->device->compiler)) {
pipeline->shared_consts = (struct tu_push_constant_range) {
.lo = 0,
.dwords = builder->layout->push_constant_size / 4,
VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT;
}
- if (layout->push_constant_size > 0) {
+ if (tu6_shared_constants_enable(layout, dev->compiler)) {
pipeline->shared_consts = (struct tu_push_constant_range) {
.lo = 0,
.dwords = layout->push_constant_size / 4,
#define MAX_VIEWPORT_SIZE (1 << 14)
#define MAX_SCISSORS 16
#define MAX_DISCARD_RECTANGLES 4
-#define MAX_PUSH_CONSTANTS_SIZE 128
+#define MAX_PUSH_CONSTANTS_SIZE 256
#define MAX_PUSH_DESCRIPTORS 32
#define MAX_DYNAMIC_UNIFORM_BUFFERS 16
#define MAX_DYNAMIC_STORAGE_BUFFERS 8
struct tu_shader *shader,
const VkAllocationCallbacks *alloc);
+static bool inline
+tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
+ const struct ir3_compiler *compiler)
+{
+ return layout->push_constant_size > 0 &&
+ layout->push_constant_size <= (compiler->shared_consts_size * 16);
+}
+
+
struct tu_program_descriptor_linkage
{
struct ir3_const_state const_state;
lower_load_push_constant(struct tu_device *dev,
nir_builder *b,
nir_intrinsic_instr *instr,
- struct tu_shader *shader)
+ struct tu_shader *shader,
+ const struct tu_pipeline_layout *layout)
{
uint32_t base = nir_intrinsic_base(instr);
assert(base % 4 == 0);
assert(base >= shader->push_consts.lo * 4);
base -= shader->push_consts.lo * 4;
+ if (tu6_shared_constants_enable(layout, dev->compiler))
+ base += dev->compiler->shared_consts_base_offset * 4;
+
nir_ssa_def *load =
nir_load_uniform(b, instr->num_components,
instr->dest.ssa.bit_size,
nir_ushr(b, instr->src[0].ssa, nir_imm_int(b, 2)),
- .base = base + dev->compiler->shared_consts_base_offset * 4);
+ .base = base);
nir_ssa_def_rewrite_uses(&instr->dest.ssa, load);
{
switch (instr->intrinsic) {
case nir_intrinsic_load_push_constant:
- lower_load_push_constant(dev, b, instr, shader);
+ lower_load_push_constant(dev, b, instr, shader, layout);
return true;
case nir_intrinsic_load_vulkan_descriptor:
ir3_finalize_nir(dev->compiler, nir);
+ uint32_t reserved_consts_vec4 = align(shader->push_consts.dwords, 16) / 4;
+ bool shared_consts_enable = tu6_shared_constants_enable(layout, dev->compiler);
+
shader->ir3_shader =
ir3_shader_from_nir(dev->compiler, nir, &(struct ir3_shader_options) {
- .reserved_user_consts = 0,
- .shared_consts_enable = layout->push_constant_size > 0,
+ .reserved_user_consts = reserved_consts_vec4,
+ .shared_consts_enable = shared_consts_enable,
.api_wavesize = key->api_wavesize,
.real_wavesize = key->real_wavesize,
}, &so_info);