arm64: dts: renesas: r8a774c0: Add PCIe EP node

Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 4217119..10e79f2 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1698,6 +1698,25 @@
                        status = "disabled";
                };
 
+               pciec0_ep: pcie-ep@fe000000 {
+                       compatible = "renesas,r8a774c0-pcie-ep",
+                                    "renesas,rcar-gen3-pcie-ep";
+                       reg = <0x0 0xfe000000 0 0x80000>,
+                             <0x0 0xfe100000 0 0x100000>,
+                             <0x0 0xfe200000 0 0x200000>,
+                             <0x0 0x30000000 0 0x8000000>,
+                             <0x0 0x38000000 0 0x8000000>;
+                       reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 319>;
+                       clock-names = "pcie";
+                       resets = <&cpg 319>;
+                       power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+                       status = "disabled";
+               };
+
                vspb0: vsp@fe960000 {
                        compatible = "renesas,vsp2";
                        reg = <0 0xfe960000 0 0x8000>;