arm64: dts: qcom: sdm670: add cpu frequency scaling

Add CPU frequency scaling, and also add the corresponding memory and
cache bandwidths for each frequency.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20230802011548.387519-9-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 45f9633..e1ef3fc 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
@@ -35,6 +36,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_0>;
@@ -56,6 +61,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD1>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_100>;
@@ -72,6 +81,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x200>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD2>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_200>;
@@ -88,6 +101,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x300>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD3>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_300>;
@@ -104,6 +121,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x400>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD4>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_400>;
@@ -120,6 +141,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x500>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 0>;
+                       operating-points-v2 = <&cpu0_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD5>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_500>;
@@ -136,6 +161,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x600>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 1>;
+                       operating-points-v2 = <&cpu6_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD6>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_600>;
@@ -152,6 +181,10 @@
                        compatible = "qcom,kryo360";
                        reg = <0x0 0x700>;
                        enable-method = "psci";
+                       qcom,freq-domain = <&cpufreq_hw 1>;
+                       operating-points-v2 = <&cpu6_opp_table>;
+                       interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+                                       <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
                        power-domains = <&CPU_PD7>;
                        power-domain-names = "psci";
                        next-level-cache = <&L2_700>;
@@ -246,6 +279,111 @@
                reg = <0x0 0x80000000 0x0 0x0>;
        };
 
+       cpu0_opp_table: opp-table-cpu0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               cpu0_opp1: opp-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-peak-kBps = <400000 4800000>;
+               };
+
+               cpu0_opp2: opp-576000000 {
+                       opp-hz = /bits/ 64 <576000000>;
+                       opp-peak-kBps = <400000 4800000>;
+               };
+
+               cpu0_opp3: opp-748800000 {
+                       opp-hz = /bits/ 64 <748800000>;
+                       opp-peak-kBps = <1200000 4800000>;
+               };
+
+               cpu0_opp4: opp-998400000 {
+                       opp-hz = /bits/ 64 <998400000>;
+                       opp-peak-kBps = <1804000 8908800>;
+               };
+
+               cpu0_opp5: opp-1209600000 {
+                       opp-hz = /bits/ 64 <1209600000>;
+                       opp-peak-kBps = <2188000 8908800>;
+               };
+
+               cpu0_opp6: opp-1324800000 {
+                       opp-hz = /bits/ 64 <1324800000>;
+                       opp-peak-kBps = <2188000 13516800>;
+               };
+
+               cpu0_opp7: opp-1516800000 {
+                       opp-hz = /bits/ 64 <1516800000>;
+                       opp-peak-kBps = <3072000 15052800>;
+               };
+
+               cpu0_opp8: opp-1612800000 {
+                       opp-hz = /bits/ 64 <1612800000>;
+                       opp-peak-kBps = <3072000 22118400>;
+               };
+
+               cpu0_opp9: opp-1708800000 {
+                       opp-hz = /bits/ 64 <1708800000>;
+                       opp-peak-kBps = <4068000 23040000>;
+               };
+       };
+
+       cpu6_opp_table: opp-table-cpu6 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               cpu6_opp1: opp-300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       opp-peak-kBps = <400000 4800000>;
+               };
+
+               cpu6_opp2: opp-652800000 {
+                       opp-hz = /bits/ 64 <652800000>;
+                       opp-peak-kBps = <400000 4800000>;
+               };
+
+               cpu6_opp3: opp-825600000 {
+                       opp-hz = /bits/ 64 <825600000>;
+                       opp-peak-kBps = <1200000 4800000>;
+               };
+
+               cpu6_opp4: opp-979200000 {
+                       opp-hz = /bits/ 64 <979200000>;
+                       opp-peak-kBps = <1200000 4800000>;
+               };
+
+               cpu6_opp5: opp-1132800000 {
+                       opp-hz = /bits/ 64 <1132800000>;
+                       opp-peak-kBps = <2188000 8908800>;
+               };
+
+               cpu6_opp6: opp-1363200000 {
+                       opp-hz = /bits/ 64 <1363200000>;
+                       opp-peak-kBps = <4068000 12902400>;
+               };
+
+               cpu6_opp7: opp-1536000000 {
+                       opp-hz = /bits/ 64 <1536000000>;
+                       opp-peak-kBps = <4068000 12902400>;
+               };
+
+               cpu6_opp8: opp-1747200000 {
+                       opp-hz = /bits/ 64 <1747200000>;
+                       opp-peak-kBps = <4068000 15052800>;
+               };
+
+               cpu6_opp9: opp-1843200000 {
+                       opp-hz = /bits/ 64 <1843200000>;
+                       opp-peak-kBps = <4068000 15052800>;
+               };
+
+               cpu6_opp10: opp-1996800000 {
+                       opp-hz = /bits/ 64 <1996800000>;
+                       opp-peak-kBps = <6220000 19046400>;
+               };
+       };
+
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
@@ -1364,5 +1502,16 @@
 
                        #interconnect-cells = <1>;
                };
+
+               cpufreq_hw: cpufreq@17d43000 {
+                       compatible = "qcom,cpufreq-hw";
+                       reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
+                       reg-names = "freq-domain0", "freq-domain1";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
        };
 };