return m;
}
-static void disas_xtensa_insn(DisasContext *dc)
+static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
{
#define HAS_OPTION_BITS(opt) do { \
if (!option_bits_enabled(dc, opt)) { \
#define RSR_SR (b1)
- uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc);
- uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1);
+ uint8_t b0 = cpu_ldub_code(env, dc->pc);
+ uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
uint8_t b2 = 0;
static const uint32_t B4CONST[] = {
HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
} else {
dc->next_pc = dc->pc + 3;
- b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2);
+ b2 = cpu_ldub_code(env, dc->pc + 2);
}
switch (OP0) {
gen_ibreak_check(env, &dc);
}
- disas_xtensa_insn(&dc);
+ disas_xtensa_insn(env, &dc);
++insn_count;
if (dc.icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);