SDValue SelectionDAG::getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
bool ConstantFold) {
- assert(MulImm.getSignificantBits() <= VT.getSizeInBits() &&
- "Immediate does not fit VT");
-
- MulImm = MulImm.sextOrTrunc(VT.getSizeInBits());
+ assert(MulImm.getBitWidth() == VT.getSizeInBits() &&
+ "APInt size does not match type size!");
if (ConstantFold) {
const MachineFunction &MF = getMachineFunction();
if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT);
if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
- return getVScale(DL, VT, N1.getConstantOperandAPInt(0));
+ return getVScale(DL, VT,
+ N1.getConstantOperandAPInt(0).trunc(VT.getSizeInBits()));
break;
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG:
ret i32 %1
}
+define i1 @rdvl_i1() {
+; CHECK-LABEL: rdvl_i1:
+; CHECK: rdvl x8, #-1
+; CHECK-NEXT: asr x8, x8, #4
+; CHECK-NEXT: and w0, w8, #0x1
+; CHECK-NEXT: ret
+ %a = tail call i64 @llvm.vscale.i64()
+ %b = trunc i64 %a to i1
+ ret i1 %b
+}
+
;
; CNTH
;