Merge branch 'mesa_7_5_branch' into mesa_7_6_branch

Conflicts:

	Makefile
	configs/default
	progs/glsl/Makefile
	src/gallium/auxiliary/util/u_simple_shaders.c
	src/gallium/state_trackers/glx/xlib/xm_api.c
	src/mesa/drivers/dri/i965/brw_draw_upload.c
	src/mesa/drivers/dri/i965/brw_vs_emit.c
	src/mesa/drivers/dri/intel/intel_context.h
	src/mesa/drivers/dri/intel/intel_pixel.c
	src/mesa/drivers/dri/intel/intel_pixel_read.c
	src/mesa/main/texenvprogram.c
	src/mesa/main/version.h

diff --cc src/gallium/auxiliary/util/u_simple_shaders.c
index 1b8da9b,acc5b83..ab75429
--- 1/src/gallium/auxiliary/util/u_simple_shaders.c
--- 2/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@@ -131,8 -296,8 +131,6 @@@ util_make_fragment_tex_shader(struct pi
  
  
  
--
--
  /**
   * Make simple fragment color pass-through shader.
   */

diff --cc src/mesa/drivers/dri/i965/brw_context.h
Simple merge

diff --cc src/mesa/drivers/dri/i965/brw_draw.c
index 682094f,54b0661..c53bd47
--- 1/src/mesa/drivers/dri/i965/brw_draw.c
--- 2/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@@ -187,8 -185,11 +187,9 @@@ static void brw_merge_inputs( struct br
  
     for (i = 0; i < VERT_ATTRIB_MAX; i++) {
        brw->vb.inputs[i].glarray = arrays[i];
+       brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
  
        if (arrays[i]->StrideB != 0)
 -       brw->vb.info.varying |= 1 << i;
 -
         brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
            ((i%16) * 2);
     }

diff --cc src/mesa/drivers/dri/i965/brw_draw_upload.c
Simple merge

diff --cc src/mesa/drivers/dri/intel/intel_pixel_read.c
index 8713463,0370255..30b06f2
--- 1/src/mesa/drivers/dri/intel/intel_pixel_read.c
--- 2/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@@ -261,19 -261,16 +261,32 @@@ do_blit_readpixels(GLcontext * ctx
           if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
              continue;
  
++<<<<<<< HEAD:src/mesa/drivers/dri/intel/intel_pixel_read.c
 +         if (!intelEmitCopyBlit(intel,
 +                              src->cpp,
 +                              src->pitch, src->buffer, 0, src->tiling,
 +                              rowLength, dst_buffer, dst_offset, GL_FALSE,
 +                              rect.x1,
 +                              rect.y1,
 +                              rect.x1 - src_rect.x1,
 +                              rect.y2 - src_rect.y2,
 +                              rect.x2 - rect.x1, rect.y2 - rect.y1,
 +                              GL_COPY)) {
 +          UNLOCK_HARDWARE(intel);
 +          return GL_FALSE;
 +       }
++=======
+          intelEmitCopyBlit(intel,
+                            src->cpp,
+                            src->pitch, src->buffer, 0, src->tiling,
+                            rowLength, dst_buffer, dst_offset, GL_FALSE,
+                            rect.x1,
+                            rect.y1,
+                            rect.x1 - src_rect.x1,
+                            rect.y2 - src_rect.y2,
+                            rect.x2 - rect.x1, rect.y2 - rect.y1,
+                          GL_COPY);
++>>>>>>> mesa_7_5_branch:src/mesa/drivers/dri/intel/intel_pixel_read.c
        }
     }
     UNLOCK_HARDWARE(intel);

diff --cc src/mesa/drivers/dri/intel/intel_regions.c
index 068a3f3,b8d2dec..a86c66a
--- 1/src/mesa/drivers/dri/intel/intel_regions.c
--- 2/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@@ -179,23 -113,14 +179,30 @@@ intel_region_alloc(struct intel_contex
                   GLboolean expect_accelerated_upload)
  {
     dri_bo *buffer;
 +   struct intel_region *region;
 +
 +   /* If we're tiled, our allocations are in 8 or 32-row blocks, so
 +    * failure to align our height means that we won't allocate enough pages.
 +    *
 +    * If we're untiled, we still have to align to 2 rows high because the
 +    * data port accesses 2x2 blocks even if the bottom row isn't to be
 +    * rendered, so failure to align means we could walk off the end of the
 +    * GTT and fault.
 +    */
 +   if (tiling == I915_TILING_X)
 +      height = ALIGN(height, 8);
 +   else if (tiling == I915_TILING_Y)
 +      height = ALIGN(height, 32);
 +   else
 +      height = ALIGN(height, 2);
  
+    /* If we're untiled, we have to align to 2 rows high because the
+     * data port accesses 2x2 blocks even if the bottom row isn't to be
+     * rendered, so failure to align means we could walk off the end of the
+     * GTT and fault.
+     */
+    height = ALIGN(height, 2);
+ 
     if (expect_accelerated_upload) {
        buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
                                             pitch * cpp * height, 64);