}
}
-static unsigned long g12_get_ddr_freq_quick(struct ddr_bandwidth *db)
+static unsigned long g12_get_dmc_freq_quick(struct ddr_bandwidth *db)
{
unsigned int val;
unsigned int n, m, od1;
n = ((val >> 10) & 0x1f);
od1 = (((val >> 19) & 0x1)) == 1 ? 2 : 1;
if (n)
- freq = 2 * (((DEFAULT_XTAL_FREQ * m) / n) >> od1) / od_div;
+ freq = (((DEFAULT_XTAL_FREQ * m) / n) >> od1) / od_div;
return freq;
}
struct ddr_bandwidth_ops g12_ddr_bw_ops = {
.init = g12_dmc_bandwidth_init,
.config_port = g12_dmc_port_config,
- .get_freq = g12_get_ddr_freq_quick,
+ .get_freq = g12_get_dmc_freq_quick,
.handle_irq = g12_handle_irq,
.bandwidth_enable = g12_dmc_bandwidth_enable,
#if DDR_BANDWIDTH_DEBUG
}
-static unsigned long gx_get_ddr_freq_quick(struct ddr_bandwidth *db)
+static unsigned long gx_get_dmc_freq_quick(struct ddr_bandwidth *db)
{
unsigned int val;
unsigned int od, n, m, od1;
struct ddr_bandwidth_ops gx_ddr_bw_ops = {
.init = gx_dmc_bandwidth_init,
.config_port = gx_dmc_port_config,
- .get_freq = gx_get_ddr_freq_quick,
+ .get_freq = gx_get_dmc_freq_quick,
.handle_irq = gx_handle_irq,
.bandwidth_enable = gx_dmc_bandwidth_enable,
#if DDR_BANDWIDTH_DEBUG
writel(val, db->ddr_reg + port_reg[channel]);
}
-static unsigned long gxl_get_ddr_freq_quick(struct ddr_bandwidth *db)
+static unsigned long gxl_get_dmc_freq_quick(struct ddr_bandwidth *db)
{
unsigned int val;
unsigned int od, n, m, od1;
struct ddr_bandwidth_ops gxl_ddr_bw_ops = {
.init = gxl_dmc_bandwidth_init,
.config_port = gxl_dmc_port_config,
- .get_freq = gxl_get_ddr_freq_quick,
+ .get_freq = gxl_get_dmc_freq_quick,
.handle_irq = gxl_handle_irq,
.bandwidth_enable = gxl_dmc_bandwidth_enable,
#if DDR_BANDWIDTH_DEBUG