struct tg3 *tp = tnapi->tp;
prefetch(tnapi->hw_status);
- prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+ if (tnapi->rx_rcb)
+ prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
if (likely(!tg3_irq_sync(tp)))
napi_schedule(&tnapi->napi);
struct tg3 *tp = tnapi->tp;
prefetch(tnapi->hw_status);
- prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
+ if (tnapi->rx_rcb)
+ prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
/*
* Writing any value to intr-mbox-0 clears PCI INTA# and
* chip-internal interrupt pending events.
for (j = 0; j < tp->irq_cnt; j++) {
struct tg3_napi *tnapi = &tp->napi[j];
+ if (!tnapi->tx_buffers)
+ continue;
+
for (i = 0; i < TG3_TX_RING_SIZE; ) {
struct tx_ring_info *txp;
struct sk_buff *skb;
tnapi->tx_prod = 0;
tnapi->tx_cons = 0;
- memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
+ if (tnapi->tx_ring)
+ memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
tnapi->rx_rcb_ptr = 0;
- memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
+ if (tnapi->rx_rcb)
+ memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
}
return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
+ /*
+ * If multivector RSS is enabled, vector 0 does not handle
+ * rx or tx interrupts. Don't allocate any resources for it.
+ */
+ if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
+ continue;
+
tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
TG3_RX_RCB_RING_BYTES(tp),
&tnapi->rx_rcb_mapping);
struct tg3_napi *tnapi, *rnapi;
struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
- tnapi = &tp->napi[0];
- rnapi = &tp->napi[0];
+ if (tp->irq_cnt > 1) {
+ tnapi = &tp->napi[1];
+ rnapi = &tp->napi[1];
+ } else {
+ tnapi = &tp->napi[0];
+ rnapi = &tp->napi[0];
+ }
coal_now = tnapi->coal_now | rnapi->coal_now;
if (loopback_mode == TG3_MAC_LOOPBACK) {