bool prim_restart_enable = state->dynamic.primitive_restart_enable;
unsigned patch_control_points = state->graphics_pipeline->tess_patch_control_points;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
+ unsigned num_tess_patches = 0;
unsigned ia_multi_vgt_param;
+ if (radv_pipeline_has_stage(state->graphics_pipeline, MESA_SHADER_TESS_CTRL)) {
+ struct radv_shader *tcs = state->graphics_pipeline->base.shaders[MESA_SHADER_TESS_CTRL];
+ num_tess_patches = tcs->info.num_tess_patches;
+ }
+
ia_multi_vgt_param =
si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, count_from_stream_output,
draw_vertex_count, topology, prim_restart_enable,
- patch_control_points);
+ patch_control_points, num_tess_patches);
if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
if (info->gfx_level == GFX9) {
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
- if (radv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL))
- ia_multi_vgt_param.primgroup_size =
- pipeline->base.shaders[MESA_SHADER_TESS_CTRL]->info.num_tess_patches;
- else if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
- ia_multi_vgt_param.primgroup_size = 64;
- else
- ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
-
- /* GS requirement. */
- ia_multi_vgt_param.partial_es_wave = false;
- if (radv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) && pdevice->rad_info.gfx_level <= GFX8)
- if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pdevice->gs_table_depth - 3)
- ia_multi_vgt_param.partial_es_wave = true;
-
ia_multi_vgt_param.ia_switch_on_eoi = false;
if (pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
ia_multi_vgt_param.ia_switch_on_eoi = true;
}
ia_multi_vgt_param.base =
- S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(pdevice->rad_info.gfx_level == GFX8 ? 2 : 0) |
S_030960_EN_INST_OPT_BASIC(pdevice->rad_info.gfx_level >= GFX9) |
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw,
bool indirect_draw, bool count_from_stream_output,
uint32_t draw_vertex_count, unsigned topology,
- bool prim_restart_enable, unsigned patch_control_points);
+ bool prim_restart_enable, unsigned patch_control_points,
+ unsigned num_tess_patches);
void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec,
unsigned event, unsigned event_flags, unsigned dst_sel,
unsigned data_sel, uint64_t va, uint32_t new_fence,
struct radv_ia_multi_vgt_param_helpers {
uint32_t base;
bool partial_es_wave;
- uint8_t primgroup_size;
bool ia_switch_on_eoi;
bool partial_vs_wave;
};
si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw,
bool indirect_draw, bool count_from_stream_output,
uint32_t draw_vertex_count, unsigned topology, bool prim_restart_enable,
- unsigned patch_control_points)
+ unsigned patch_control_points, unsigned num_tess_patches)
{
enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
bool partial_es_wave = cmd_buffer->state.graphics_pipeline->ia_multi_vgt_param.partial_es_wave;
bool multi_instances_smaller_than_primgroup;
struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
+ unsigned primgroup_size;
+
+ if (radv_pipeline_has_stage(cmd_buffer->state.graphics_pipeline, MESA_SHADER_TESS_CTRL)) {
+ primgroup_size = num_tess_patches;
+ } else if (radv_pipeline_has_stage(cmd_buffer->state.graphics_pipeline, MESA_SHADER_GEOMETRY)) {
+ primgroup_size = 64;
+ } else {
+ primgroup_size = 128; /* recommended without a GS */
+ }
+
+ /* GS requirement. */
+ if (radv_pipeline_has_stage(cmd_buffer->state.graphics_pipeline, MESA_SHADER_GEOMETRY) &&
+ gfx_level <= GFX8) {
+ unsigned gs_table_depth = cmd_buffer->device->physical_device->gs_table_depth;
+ if (SI_GS_PER_ES / primgroup_size >= gs_table_depth - 3)
+ partial_es_wave = true;
+ }
if (radv_pipeline_has_stage(cmd_buffer->state.graphics_pipeline, MESA_SHADER_TESS_CTRL)) {
if (topology == V_008958_DI_PT_PATCH) {
multi_instances_smaller_than_primgroup = indirect_draw;
if (!multi_instances_smaller_than_primgroup && instanced_draw) {
uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
- if (num_prims < cmd_buffer->state.graphics_pipeline->ia_multi_vgt_param.primgroup_size)
+ if (num_prims < primgroup_size)
multi_instances_smaller_than_primgroup = true;
}
}
return cmd_buffer->state.graphics_pipeline->ia_multi_vgt_param.base |
+ S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |