drm/i915/pps: move pps code over from intel_display.c and refactor

intel_display.c has some pps functions that belong to intel_pps.c. Move
them over.

While at it, refactor the duplicate intel_pps_init() in intel_display.c
into an orthogonal intel_pps_setup() in intel_pps.c, and call it earlier
in intel_modeset_init_nogem().

Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-2-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 32ff9d2..16f3f47 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -83,6 +83,7 @@
 #include "intel_overlay.h"
 #include "intel_pipe_crc.h"
 #include "intel_pm.h"
+#include "intel_pps.h"
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_sideband.h"
@@ -13795,48 +13796,12 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
        return true;
 }
 
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
-{
-       int pps_num;
-       int pps_idx;
-
-       if (HAS_DDI(dev_priv))
-               return;
-       /*
-        * This w/a is needed at least on CPT/PPT, but to be sure apply it
-        * everywhere where registers can be write protected.
-        */
-       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-               pps_num = 2;
-       else
-               pps_num = 1;
-
-       for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
-               u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
-
-               val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
-               intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
-       }
-}
-
-static void intel_pps_init(struct drm_i915_private *dev_priv)
-{
-       if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
-               dev_priv->pps_mmio_base = PCH_PPS_BASE;
-       else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-               dev_priv->pps_mmio_base = VLV_PPS_BASE;
-       else
-               dev_priv->pps_mmio_base = PPS_BASE;
-
-       intel_pps_unlock_regs_wa(dev_priv);
-}
-
 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 {
        struct intel_encoder *encoder;
        bool dpd_is_edp = false;
 
-       intel_pps_init(dev_priv);
+       intel_pps_unlock_regs_wa(dev_priv);
 
        if (!HAS_DISPLAY(dev_priv))
                return;
@@ -14848,6 +14813,8 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
 
        intel_panel_sanitize_ssc(i915);
 
+       intel_pps_setup(i915);
+
        intel_gmbus_setup(i915);
 
        drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bb72de1..64ffa34 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -546,7 +546,6 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 int intel_display_suspend(struct drm_device *dev);
-void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index da6ee0b..69d9d41 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1370,3 +1370,37 @@ void intel_pps_init(struct intel_dp *intel_dp)
 
        intel_pps_encoder_reset(intel_dp);
 }
+
+void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
+{
+       int pps_num;
+       int pps_idx;
+
+       if (HAS_DDI(dev_priv))
+               return;
+       /*
+        * This w/a is needed at least on CPT/PPT, but to be sure apply it
+        * everywhere where registers can be write protected.
+        */
+       if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+               pps_num = 2;
+       else
+               pps_num = 1;
+
+       for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
+               u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
+
+               val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
+               intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
+       }
+}
+
+void intel_pps_setup(struct drm_i915_private *i915)
+{
+       if (HAS_PCH_SPLIT(i915) || IS_GEN9_LP(i915))
+               i915->pps_mmio_base = PCH_PPS_BASE;
+       else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+               i915->pps_mmio_base = VLV_PPS_BASE;
+       else
+               i915->pps_mmio_base = PPS_BASE;
+}

diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h
index 22045c5..fbbcca7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pps.h
+++ b/drivers/gpu/drm/i915/display/intel_pps.h
@@ -46,4 +46,7 @@ void intel_pps_reset_all(struct drm_i915_private *i915);
 void vlv_pps_init(struct intel_encoder *encoder,
                  const struct intel_crtc_state *crtc_state);
 
+void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
+void intel_pps_setup(struct drm_i915_private *i915);
+
 #endif /* __INTEL_PPS_H__ */

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f5666b4..b37b189 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -58,6 +58,7 @@
 #include "display/intel_hotplug.h"
 #include "display/intel_overlay.h"
 #include "display/intel_pipe_crc.h"
+#include "display/intel_pps.h"
 #include "display/intel_sprite.h"
 #include "display/intel_vga.h"