--- /dev/null
+* SPEAr Shared IRQ layer (shirq)
+
+SPEAr3xx architecture includes shared/multiplexed irqs for certain set
+of devices. The multiplexor provides a single interrupt to parent
+interrupt controller (VIC) on behalf of a group of devices.
+
+There can be multiple groups available on SPEAr3xx variants but not
+exceeding 4. The number of devices in a group can differ, further they
+may share same set of status/mask registers spanning across different
+bit masks. Also in some cases the group may not have enable or other
+registers. This makes software little complex.
+
+A single node in the device tree is used to describe the shared
+interrupt multiplexor (one node for all groups). A group in the
+interrupt controller shares config/control registers with other groups.
+For example, a 32-bit interrupt enable/disable config register can
+accommodate upto 4 interrupt groups.
+
+Required properties:
+ - compatible: should be, either of
+ - "st,spear300-shirq"
+ - "st,spear310-shirq"
+ - "st,spear320-shirq"
+ - interrupt-controller: Identifies the node as an interrupt controller.
+ - #interrupt-cells: should be <1> which basically contains the offset
+ (starting from 0) of interrupts for all the groups.
+ - reg: Base address and size of shirq registers.
+ - interrupts: The list of interrupts generated by the groups which are
+ then connected to a parent interrupt controller. Each group is
+ associated with one of the interrupts, hence number of interrupts (to
+ parent) is equal to number of groups. The format of the interrupt
+ specifier depends in the interrupt parent controller.
+
+ Optional properties:
+ - interrupt-parent: pHandle of the parent interrupt controller, if not
+ inherited from the parent node.
+
+Example:
+
+The following is an example from the SPEAr320 SoC dtsi file.
+
+shirq: interrupt-controller@0xb3000000 {
+ compatible = "st,spear320-shirq";
+ reg = <0xb3000000 0x1000>;
+ interrupts = <28 29 30 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+};
spear1340-evb.dtb
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear310-evb.dtb \
- spear320-evb.dtb
+ spear320-evb.dtb \
+ spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-cubieboard.dtb \
sun5i-olinuxino.dtb
pinctrl-0 = <&state_default>;
state_default: pinmux {
- i2c0-pmx {
+ i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
+ i2s0 {
+ st,pins = "i2s0_grp";
+ st,function = "i2s0";
+ };
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
+ clcd {
+ st,pins = "clcd_grp" , "clcd_high_res";
+ st,function = "clcd";
+ };
eth {
st,pins = "gmii_grp";
st,function = "gmii";
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
- pci {
- st,pins = "pcie0_grp","pcie1_grp",
- "pcie2_grp";
- st,function = "pci";
- };
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
"nand_16bit_grp";
st,function = "nand";
};
+ sata {
+ st,pins = "sata0_grp";
+ st,function = "sata";
+ };
+ pcie {
+ st,pins = "pcie1_grp", "pcie2_grp";
+ st,function = "pci_express";
+ };
};
};
fsmc: flash@b0000000 {
status = "okay";
+
+ partition@0 {
+ label = "xloader";
+ reg = <0x0 0x80000>;
+ };
+ partition@80000 {
+ label = "u-boot";
+ reg = <0x80000 0x140000>;
+ };
+ partition@1C0000 {
+ label = "environment";
+ reg = <0x1C0000 0x40000>;
+ };
+ partition@200000 {
+ label = "dtb";
+ reg = <0x200000 0x40000>;
+ };
+ partition@240000 {
+ label = "linux";
+ reg = <0x240000 0xC00000>;
+ };
+ partition@E40000 {
+ label = "rootfs";
+ reg = <0xE40000 0x0>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@1 {
+ label = "wakeup";
+ linux,code = <0x100>;
+ gpios = <&gpio0 7 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
};
gmac0: eth@e2000000 {
+ phy-mode = "gmii";
status = "okay";
};
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
+ };
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
};
- partition@50000 {
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
- spi0: spi@e0100000 {
- status = "okay";
- };
-
ehci@e4800000 {
status = "okay";
};
status = "okay";
};
- i2c1: i2c@5cd00000 {
- status = "okay";
- };
-
kbd@e0300000 {
linux,keymap = < 0x00000001
0x00010002
0x08080052 >;
autorepeat;
st,mode = <0>;
+ suspended_rate = <2000000>;
status = "okay";
};
serial@e0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ spi0: spi@e0100000 {
+ status = "okay";
+ num-cs = <3>;
+ cs-gpios = <&gpio1 7 0>, <&spics 0>, <&spics 1>;
+
+ stmpe610@0 {
+ compatible = "st,stmpe610";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x7>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ interrupts = <6 0x4>;
+ interrupt-parent = <&gpio1>;
+ irq-trigger = <0x2>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <2>;
+ ts,settling = <2>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+
+ m25p80@1 {
+ compatible = "st,m25p80";
+ reg = <1>;
+ spi-max-frequency = <12000000>;
+ spi-cpol;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+
+ spidev@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
};
wdt@ec800620 {
compatible = "st,spear1310";
ahb {
+ spics: spics@e0700000{
+ compatible = "st,spear-spics-gpio";
+ reg = <0xe0700000 0x1000>;
+ st-spics,peripcfg-reg = <0x3b0>;
+ st-spics,sw-enable-bit = <12>;
+ st-spics,cs-value-bit = <11>;
+ st-spics,cs-enable-mask = <3>;
+ st-spics,cs-enable-shift = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
reg = <0x5c400000 0x8000>;
interrupts = <0 95 0x4>;
interrupt-names = "macirq";
+ phy-mode = "mii";
status = "disabled";
};
reg = <0x5c500000 0x8000>;
interrupts = <0 96 0x4>;
interrupt-names = "macirq";
+ phy-mode = "mii";
status = "disabled";
};
reg = <0x5c600000 0x8000>;
interrupts = <0 97 0x4>;
interrupt-names = "macirq";
+ phy-mode = "rmii";
status = "disabled";
};
reg = <0x5c700000 0x8000>;
interrupts = <0 98 0x4>;
interrupt-names = "macirq";
+ phy-mode = "rgmii";
status = "disabled";
};
#gpio-range-cells = <2>;
};
- spi1: spi@5d400000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x5d400000 0x1000>;
- interrupts = <0 99 0x4>;
- status = "disabled";
- };
-
apb {
i2c1: i2c@5cd00000 {
#address-cells = <1>;
status = "disabled";
};
+ spi1: spi@5d400000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x5d400000 0x1000>;
+ interrupts = <0 99 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
serial@5c800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x5c800000 0x1000>;
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
- kbd {
- st,pins = "keyboard_row_col_grp",
- "keyboard_col5_grp";
- st,function = "keyboard";
- };
uart0 {
- st,pins = "uart0_grp", "uart0_enh_grp";
+ st,pins = "uart0_grp";
st,function = "uart0";
};
- i2c0-pmx {
+ i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
- i2c1-pmx {
+ i2c1 {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
st,function = "spdif_out";
};
ssp0 {
- st,pins = "ssp0_grp", "ssp0_cs1_grp",
- "ssp0_cs3_grp";
+ st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
st,function = "ssp0";
};
- pwm {
- st,pins = "pwm2_grp", "pwm3_grp";
- st,function = "pwm";
- };
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
+ cam0 {
+ st,pins = "cam0_grp";
+ st,function = "cam0";
+ };
+ cam1 {
+ st,pins = "cam1_grp";
+ st,function = "cam1";
+ };
+ cam2 {
+ st,pins = "cam2_grp";
+ st,function = "cam2";
+ };
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
st,pins = "sata_grp";
st,function = "sata";
};
+ pcie {
+ st,pins = "pcie_grp";
+ st,function = "pcie";
+ };
+
};
};
+ ahci@b1000000 {
+ status = "okay";
+ };
+
dma@ea800000 {
status = "okay";
};
fsmc: flash@b0000000 {
status = "okay";
+
+ partition@0 {
+ label = "xloader";
+ reg = <0x0 0x200000>;
+ };
+ partition@200000 {
+ label = "u-boot";
+ reg = <0x200000 0x200000>;
+ };
+ partition@400000 {
+ label = "environment";
+ reg = <0x400000 0x100000>;
+ };
+ partition@500000 {
+ label = "dtb";
+ reg = <0x500000 0x100000>;
+ };
+ partition@600000 {
+ label = "linux";
+ reg = <0x600000 0xC00000>;
+ };
+ partition@1200000 {
+ label = "rootfs";
+ reg = <0x1200000 0x0>;
+ };
};
gmac0: eth@e2000000 {
+ phy-mode = "rgmii";
status = "okay";
};
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
+ };
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
};
- partition@50000 {
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
- spi0: spi@e0100000 {
+ ehci@e4800000 {
status = "okay";
};
- ehci@e4800000 {
- status = "okay";
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@1 {
+ label = "wakeup";
+ linux,code = <0x100>;
+ gpios = <&gpio1 1 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
};
ehci@e5800000 {
status = "okay";
};
+ i2s0: i2s-play@b2400000 {
+ status = "okay";
+ };
+
+ i2s1: i2s-rec@b2000000 {
+ status = "okay";
+ };
+
+ incodec: dir-hifi {
+ compatible = "dummy,dir-hifi";
+ status = "okay";
+ };
+
ohci@e4000000 {
status = "okay";
};
status = "okay";
};
+ outcodec: dit-hifi {
+ compatible = "dummy,dit-hifi";
+ status = "okay";
+ };
+
+ sound {
+ compatible = "spear,spear-evb";
+ audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
+ audio-codecs = <&incodec &outcodec &sta529 &sta529>;
+ codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
+ stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
+ dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
+ nr_controllers = <4>;
+ status = "okay";
+ };
+
+ spdif0: spdif-in@d0100000 {
+ status = "okay";
+ };
+
+ spdif1: spdif-out@d0000000 {
+ status = "okay";
+ };
+
apb {
adc@e0080000 {
status = "okay";
};
+ i2s-play@b2400000 {
+ status = "okay";
+ };
+
+ i2s-rec@b2000000 {
+ status = "okay";
+ };
+
gpio0: gpio@e0600000 {
status = "okay";
};
i2c0: i2c@e0280000 {
status = "okay";
+
+ sta529: sta529@1a {
+ compatible = "st,sta529";
+ reg = <0x1a>;
+ };
};
i2c1: i2c@b4000000 {
status = "okay";
+
+ eeprom0@56 {
+ compatible = "st,eeprom";
+ reg = <0x56>;
+ };
+
+ stmpe801@41 {
+ compatible = "st,stmpe801";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ interrupts = <4 0x4>;
+ interrupt-parent = <&gpio0>;
+ irq-trigger = <0x2>;
+
+ stmpegpio: stmpe_gpio {
+ compatible = "st,stmpe-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
};
kbd@e0300000 {
0x08080052 >;
autorepeat;
st,mode = <0>;
+ suspended_rate = <2000000>;
status = "okay";
};
serial@e0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b4100000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ spi0: spi@e0100000 {
+ status = "okay";
+ num-cs = <3>;
+ cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
+ <&gpiopinctrl 85 0>;
+
+ m25p80@0 {
+ compatible = "m25p80";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ spi-cpol;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+
+ stmpe610@1 {
+ compatible = "st,stmpe610";
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ reg = <1>;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x7>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ interrupts = <100 0>;
+ interrupt-parent = <&gpiopinctrl>;
+ irq-trigger = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <2>;
+ ts,settling = <2>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+
+ spidev@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+ spi-cpha;
+ pl022,hierarchy = <0>;
+ pl022,interface = <0>;
+ pl022,slave-tx-disable;
+ pl022,com-mode = <0x2>;
+ pl022,rx-level-trig = <0>;
+ pl022,tx-level-trig = <0>;
+ pl022,ctrl-len = <0x11>;
+ pl022,wait-state = <0>;
+ pl022,duplex = <0>;
+ };
+ };
+
+ timer@ec800600 {
+ status = "okay";
};
wdt@ec800620 {
compatible = "st,spear1340";
ahb {
+
+ spics: spics@e0700000{
+ compatible = "st,spear-spics-gpio";
+ reg = <0xe0700000 0x1000>;
+ st-spics,peripcfg-reg = <0x42c>;
+ st-spics,sw-enable-bit = <21>;
+ st-spics,cs-value-bit = <20>;
+ st-spics,cs-enable-mask = <3>;
+ st-spics,cs-enable-shift = <18>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
status = "disabled";
};
+ i2s-play@b2400000 {
+ compatible = "snps,designware-i2s";
+ reg = <0xb2400000 0x10000>;
+ interrupt-names = "play_irq";
+ interrupts = <0 98 0x4
+ 0 99 0x4>;
+ play;
+ channel = <8>;
+ status = "disabled";
+ };
+
+ i2s-rec@b2000000 {
+ compatible = "snps,designware-i2s";
+ reg = <0xb2000000 0x10000>;
+ interrupt-names = "record_irq";
+ interrupts = <0 100 0x4
+ 0 101 0x4>;
+ record;
+ channel = <8>;
+ status = "disabled";
+ };
+
pinmux: pinmux@e0700000 {
compatible = "st,spear1340-pinmux";
reg = <0xe0700000 0x1000>;
#gpio-range-cells = <2>;
};
+ pwm: pwm@e0180000 {
+ compatible ="st,spear13xx-pwm";
+ reg = <0xe0180000 0x1000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ spdif-in@d0100000 {
+ compatible = "st,spdif-in";
+ reg = < 0xd0100000 0x20000
+ 0xd0110000 0x10000 >;
+ interrupts = <0 84 0x4>;
+ status = "disabled";
+ };
+
+ spdif-out@d0000000 {
+ compatible = "st,spdif-out";
+ reg = <0xd0000000 0x20000>;
+ interrupts = <0 85 0x4>;
+ status = "disabled";
+ };
+
spi1: spi@5d400000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x5d400000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 99 0x4>;
status = "disabled";
};
compatible = "snps,designware-i2c";
reg = <0xb4000000 0x1000>;
interrupts = <0 104 0x4>;
+ write-16bit;
status = "disabled";
};
bootargs = "console=ttyAMA0,115200";
};
+ cpufreq {
+ compatible = "st,cpufreq-spear";
+ cpufreq_tbl = < 166000
+ 200000
+ 250000
+ 300000
+ 400000
+ 500000
+ 600000 >;
+ status = "disable";
+ };
+
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
+ 0xd0000000 0xd0000000 0x02000000
+ 0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
sdhci@b3000000 {
cf@b2800000 {
compatible = "arasan,cf-spear1340";
- reg = <0xb2800000 0x100>;
+ reg = <0xb2800000 0x1000>;
interrupts = <0 29 0x4>;
status = "disabled";
};
0 23 0x4>;
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
+ st,mode = <2>;
status = "disabled";
};
status = "disabled";
};
+ pcm {
+ compatible = "st,pcm-audio";
+ #address-cells = <0>;
+ #size-cells = <0>;
+ status = "disable";
+ };
+
smi: flash@ea000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
status = "disabled";
};
- spi0: spi@e0100000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0xe0100000 0x1000>;
- interrupts = <0 31 0x4>;
- status = "disabled";
- };
-
ehci@e4800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe4800000 0x1000>;
interrupts = <0 64 0x4>;
+ usbh0_id = <0>;
status = "disabled";
};
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe5800000 0x1000>;
interrupts = <0 66 0x4>;
+ usbh1_id = <1>;
status = "disabled";
};
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe4000000 0x1000>;
interrupts = <0 65 0x4>;
+ usbh0_id = <0>;
status = "disabled";
};
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe5000000 0x1000>;
interrupts = <0 67 0x4>;
+ usbh1_id = <1>;
status = "disabled";
};
compatible = "simple-bus";
ranges = <0x50000000 0x50000000 0x10000000
0xb0000000 0xb0000000 0x10000000
+ 0xd0000000 0xd0000000 0x02000000
+ 0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
gpio0: gpio@e0600000 {
status = "disabled";
};
+ i2s@e0180000 {
+ compatible = "st,designware-i2s";
+ reg = <0xe0180000 0x1000>;
+ interrupt-names = "play_irq", "record_irq";
+ interrupts = <0 10 0x4
+ 0 11 0x4 >;
+ status = "disabled";
+ };
+
+ i2s@e0200000 {
+ compatible = "st,designware-i2s";
+ reg = <0xe0200000 0x1000>;
+ interrupt-names = "play_irq", "record_irq";
+ interrupts = <0 26 0x4
+ 0 53 0x4>;
+ status = "disabled";
+ };
+
+ spi0: spi@e0100000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0xe0100000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 31 0x4>;
+ status = "disabled";
+ };
+
rtc@e0580000 {
- compatible = "st,spear-rtc";
+ compatible = "st,spear600-rtc";
reg = <0xe0580000 0x1000>;
interrupts = <0 36 0x4>;
status = "disabled";
adc@e0080000 {
compatible = "st,spear600-adc";
reg = <0xe0080000 0x1000>;
- interrupts = <0 44 0x4>;
+ interrupts = <0 12 0x4>;
status = "disabled";
};
timer@ec800600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xec800600 0x20>;
- interrupts = <1 13 0x301>;
+ interrupts = <1 13 0x4>;
+ status = "disabled";
};
wdt@ec800620 {
thermal@e07008c4 {
compatible = "st,thermal-spear1340";
reg = <0xe07008c4 0x4>;
+ thermal_flags = <0x7000>;
};
};
};
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition@50000 {
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
serial@d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt@fc880000 {
};
clcd@60000000 {
- compatible = "arm,clcd-pl110", "arm,primecell";
+ compatible = "arm,pl110", "arm,primecell";
reg = <0x60000000 0x1000>;
interrupts = <30>;
status = "disabled";
status = "disabled";
};
+ shirq: interrupt-controller@0x50000000 {
+ compatible = "st,spear300-shirq";
+ reg = <0x50000000 0x1000>;
+ interrupts = <28>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xa9000000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
kbd@a0000000 {
compatible = "st,spear300-kbd";
reg = <0xa0000000 0x1000>;
+ interrupts = <7>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
};
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition@50000 {
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
serial@d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b2000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b2080000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b2100000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b2180000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@b2200000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt@fc880000 {
status = "disabled";
};
+ shirq: interrupt-controller@0xb4000000 {
+ compatible = "st,spear310-shirq";
+ reg = <0xb4000000 0x1000>;
+ interrupts = <28 29 30 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
serial@b2000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2000000 0x1000>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@b2080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2080000 0x1000>;
+ interrupts = <9>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@b2100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2100000 0x1000>;
+ interrupts = <10>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@b2180000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2180000 0x1000>;
+ interrupts = <11>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@b2200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2200000 0x1000>;
+ interrupts = <12>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
st,function = "mii2";
};
pwm0_1 {
- st,pins = "pwm0_1_pin_14_15_grp";
+ st,pins = "pwm0_1_pin_37_38_grp";
st,function = "pwm0_1";
};
- pwm2 {
- st,pins = "pwm2_pin_13_grp";
- st,function = "pwm2";
- };
};
};
- clcd@90000000 {
- status = "okay";
- };
-
dma@fc400000 {
status = "okay";
};
};
sdhci@70000000 {
+ power-gpio = <&gpiopinctrl 61 1>;
status = "okay";
};
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
+ };
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
};
- partition@50000 {
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
serial@d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@a3000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@a4000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
wdt@fc880000 {
--- /dev/null
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+ model = "ST SPEAr320 HMI Board";
+ compatible = "st,spear320-hmi", "st,spear320";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ reg = <0 0x40000000>;
+ };
+
+ ahb {
+ pinmux@b3000000 {
+ st,pinmux-mode = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ i2c0 {
+ st,pins = "i2c0_grp";
+ st,function = "i2c0";
+ };
+ ssp0 {
+ st,pins = "ssp0_grp";
+ st,function = "ssp0";
+ };
+ uart0 {
+ st,pins = "uart0_grp";
+ st,function = "uart0";
+ };
+ clcd {
+ st,pins = "clcd_grp";
+ st,function = "clcd";
+ };
+ fsmc {
+ st,pins = "fsmc_8bit_grp";
+ st,function = "fsmc";
+ };
+ sdhci {
+ st,pins = "sdhci_cd_12_grp";
+ st,function = "sdhci";
+ };
+ i2s {
+ st,pins = "i2s_grp";
+ st,function = "i2s";
+ };
+ uart1 {
+ st,pins = "uart1_grp";
+ st,function = "uart1";
+ };
+ uart2 {
+ st,pins = "uart2_grp";
+ st,function = "uart2";
+ };
+ can0 {
+ st,pins = "can0_grp";
+ st,function = "can0";
+ };
+ can1 {
+ st,pins = "can1_grp";
+ st,function = "can1";
+ };
+ mii0_1 {
+ st,pins = "rmii0_1_grp";
+ st,function = "mii0_1";
+ };
+ pwm0_1 {
+ st,pins = "pwm0_1_pin_37_38_grp";
+ st,function = "pwm0_1";
+ };
+ pwm2 {
+ st,pins = "pwm2_pin_34_grp";
+ st,function = "pwm2";
+ };
+ };
+ };
+
+ clcd@90000000 {
+ status = "okay";
+ };
+
+ dma@fc400000 {
+ status = "okay";
+ };
+
+ ehci@e1800000 {
+ status = "okay";
+ };
+
+ fsmc: flash@4c000000 {
+ status = "okay";
+
+ partition@0 {
+ label = "xloader";
+ reg = <0x0 0x80000>;
+ };
+ partition@80000 {
+ label = "u-boot";
+ reg = <0x80000 0x140000>;
+ };
+ partition@1C0000 {
+ label = "environment";
+ reg = <0x1C0000 0x40000>;
+ };
+ partition@200000 {
+ label = "dtb";
+ reg = <0x200000 0x40000>;
+ };
+ partition@240000 {
+ label = "linux";
+ reg = <0x240000 0xC00000>;
+ };
+ partition@E40000 {
+ label = "rootfs";
+ reg = <0xE40000 0x0>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@1 {
+ label = "user button 1";
+ linux,code = <0x100>;
+ gpios = <&stmpegpio 3 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+
+ button@2 {
+ label = "user button 2";
+ linux,code = <0x200>;
+ gpios = <&stmpegpio 2 0x4>;
+ debounce-interval = <20>;
+ gpio-key,wakeup = <1>;
+ };
+ };
+
+ ohci@e1900000 {
+ status = "okay";
+ };
+
+ ohci@e2100000 {
+ status = "okay";
+ };
+
+ pwm: pwm@a8000000 {
+ status = "okay";
+ };
+
+ sdhci@70000000 {
+ power-gpio = <&gpiopinctrl 50 1>;
+ power_always_enb;
+ status = "okay";
+ };
+
+ smi: flash@fc000000 {
+ status = "okay";
+ clock-rate=<50000000>;
+
+ flash@f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xf8000000 0x800000>;
+ st,smi-fast-mode;
+
+ partition@0 {
+ label = "xloader";
+ reg = <0x0 0x10000>;
+ };
+ partition@10000 {
+ label = "u-boot";
+ reg = <0x10000 0x50000>;
+ };
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
+ label = "linux";
+ reg = <0x80000 0x310000>;
+ };
+ partition@390000 {
+ label = "rootfs";
+ reg = <0x390000 0x0>;
+ };
+ };
+ };
+
+ spi0: spi@d0100000 {
+ status = "okay";
+ };
+
+ spi1: spi@a5000000 {
+ status = "okay";
+ };
+
+ spi2: spi@a6000000 {
+ status = "okay";
+ };
+
+ usbd@e1100000 {
+ status = "okay";
+ };
+
+ apb {
+ gpio0: gpio@fc980000 {
+ status = "okay";
+ };
+
+ gpio@b3000000 {
+ status = "okay";
+ };
+
+ i2c0: i2c@d0180000 {
+ status = "okay";
+
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ irq-over-gpio;
+ irq-gpios = <&gpiopinctrl 29 0x4>;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+
+ stmpegpio: stmpe-gpio {
+ compatible = "stmpe,gpio";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,norequest-mask = <0xF3>;
+ };
+
+ stmpe610-ts {
+ compatible = "stmpe,ts";
+ reg = <0>;
+ ts,sample-time = <4>;
+ ts,mod-12b = <1>;
+ ts,ref-sel = <0>;
+ ts,adc-freq = <1>;
+ ts,ave-ctrl = <1>;
+ ts,touch-det-delay = <3>;
+ ts,settling = <4>;
+ ts,fraction-z = <7>;
+ ts,i-drive = <1>;
+ };
+ };
+ };
+
+ i2c1: i2c@a7000000 {
+ status = "okay";
+ };
+
+ rtc@fc900000 {
+ status = "okay";
+ };
+
+ serial@d0000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ serial@a3000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ serial@a4000000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ wdt@fc880000 {
+ status = "okay";
+ };
+ };
+ };
+};
};
clcd@90000000 {
- compatible = "arm,clcd-pl110", "arm,primecell";
+ compatible = "arm,pl110", "arm,primecell";
reg = <0x90000000 0x1000>;
- interrupts = <33>;
+ interrupts = <8>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
sdhci@70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
- interrupts = <29>;
+ interrupts = <10>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
+ shirq: interrupt-controller@0xb3000000 {
+ compatible = "st,spear320-shirq";
+ reg = <0xb3000000 0x1000>;
+ interrupts = <30 28 29 1>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
spi1: spi@a5000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa5000000 0x1000>;
+ interrupts = <15>;
+ interrupt-parent = <&shirq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
spi2: spi@a6000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa6000000 0x1000>;
+ interrupts = <16>;
+ interrupt-parent = <&shirq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
+ pwm: pwm@a8000000 {
+ compatible ="st,spear-pwm";
+ reg = <0xa8000000 0x1000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- ranges = <0xa0000000 0xa0000000 0x10000000
+ ranges = <0xa0000000 0xa0000000 0x20000000
0xd0000000 0xd0000000 0x30000000>;
i2c1: i2c@a7000000 {
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xa7000000 0x1000>;
+ interrupts = <21>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@a3000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa3000000 0x1000>;
+ interrupts = <13>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
serial@a4000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa4000000 0x1000>;
+ interrupts = <14>;
+ interrupt-parent = <&shirq>;
status = "disabled";
};
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";
+ phy-mode = "mii";
status = "disabled";
};
compatible = "arm,pl022", "arm,primecell";
reg = <0xd0100000 0x1000>;
interrupts = <20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
};
rtc@fc900000 {
- compatible = "st,spear-rtc";
+ compatible = "st,spear600-rtc";
reg = <0xfc900000 0x1000>;
interrupts = <10>;
status = "disabled";
};
ahb {
+ clcd@fc200000 {
+ status = "okay";
+ };
+
dma@fc400000 {
status = "okay";
};
+ ehci@e1800000 {
+ status = "okay";
+ };
+
+ ehci@e2000000 {
+ status = "okay";
+ };
+
gmac: ethernet@e0800000 {
phy-mode = "gmii";
status = "okay";
};
+ ohci@e1900000 {
+ status = "okay";
+ };
+
+ ohci@e2100000 {
+ status = "okay";
+ };
+
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
};
partition@10000 {
label = "u-boot";
- reg = <0x10000 0x40000>;
+ reg = <0x10000 0x50000>;
};
- partition@50000 {
+ partition@60000 {
+ label = "environment";
+ reg = <0x60000 0x10000>;
+ };
+ partition@70000 {
+ label = "dtb";
+ reg = <0x70000 0x10000>;
+ };
+ partition@80000 {
label = "linux";
- reg = <0x50000 0x2c0000>;
+ reg = <0x80000 0x310000>;
};
- partition@310000 {
+ partition@390000 {
label = "rootfs";
- reg = <0x310000 0x4f0000>;
+ reg = <0x390000 0x0>;
};
};
};
apb {
serial@d0000000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
};
serial@d0080000 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <>;
+ };
+
+ rtc@fc900000 {
+ status = "okay";
};
i2c@d0200000 {
#interrupt-cells = <1>;
};
+ clcd@fc200000 {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0xfc200000 0x1000>;
+ interrupt-parent = <&vic1>;
+ interrupts = <12>;
+ status = "disabled";
+ };
+
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <24 23>;
interrupt-names = "macirq", "eth_wake_irq";
+ phy-mode = "gmii";
status = "disabled";
};
status = "disabled";
};
+ rtc@fc900000 {
+ compatible = "st,spear600-rtc";
+ reg = <0xfc900000 0x1000>;
+ interrupts = <10>;
+ status = "disabled";
+ };
+
timer@f0000000 {
compatible = "st,spear-timer";
reg = <0xf0000000 0x400>;
#define DMAC1_BASE UL(0xEB000000)
#define MCIF_CF_BASE UL(0xB2800000)
-/* Devices present in SPEAr1310 */
-#ifdef CONFIG_MACH_SPEAR1310
-#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
-#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
-#define SPEAR1310_RAS_BASE UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
-#endif /* CONFIG_MACH_SPEAR1310 */
-
/* Debug uart for linux, will be used for debug and uncompress messages */
#define SPEAR_DBG_UART_BASE UART_BASE
#define VA_SPEAR_DBG_UART_BASE VA_UART_BASE
#include <linux/amba/pl022.h>
#include <linux/of_platform.h>
+#include <linux/pata_arasan_cf_data.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#define SPEAR1310_SATA1_BASE UL(0xB1800000)
#define SPEAR1310_SATA2_BASE UL(0xB4000000)
+#define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
+#define SPEAR1310_RAS_BASE UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
+
+static struct arasan_cf_pdata cf_pdata = {
+ .cf_if_clk = CF_IF_CLK_166M,
+ .quirk = CF_BROKEN_UDMA,
+ .dma_priv = &cf_dma_priv,
+};
+
/* ssp device registration */
static struct pl022_ssp_controller ssp1_plat_data = {
- .bus_id = 0,
.enable_dma = 0,
- .num_chipselect = 3,
};
/* Add SPEAr1310 auxdata to pass platform data */
static struct of_dev_auxdata spear1310_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_dma_priv),
+ OF_DEV_AUXDATA("arasan,cf-spear1340", MCIF_CF_BASE, NULL, &cf_pdata),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC0_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("snps,dma-spear1340", DMAC1_BASE, NULL, &dmac_plat_data),
OF_DEV_AUXDATA("arm,pl022", SSP_BASE, NULL, &pl022_plat_data),
};
struct pl022_ssp_controller pl022_plat_data = {
- .bus_id = 0,
.enable_dma = 1,
.dma_filter = dw_dma_filter,
.dma_rx_param = &ssp_dma_param[1],
.dma_tx_param = &ssp_dma_param[0],
- .num_chipselect = 3,
};
/* CF device registration */
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
-/* FIXME: probe all these from DT */
-#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
-#define SPEAR3XX_IRQ_GEN_RAS_1 28
-#define SPEAR3XX_IRQ_GEN_RAS_2 29
-#define SPEAR3XX_IRQ_GEN_RAS_3 30
-#define SPEAR3XX_IRQ_VIC_END 32
-#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
-
-#define NR_IRQS 160
+#define NR_IRQS 256
#endif /* __MACH_IRQS_H */
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG 0x54
-#define SPEAR300_INT_STS_MASK_REG 0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
-
-#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
-
-
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR300_VIRQ_IT_PERS_S,
- .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
- .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_IT_CHANGE_S,
- .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
- .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_I2S,
- .enb_mask = SPEAR300_I2S_IRQ_MASK,
- .status_mask = SPEAR300_I2S_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_TDM,
- .enb_mask = SPEAR300_TDM_IRQ_MASK,
- .status_mask = SPEAR300_TDM_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_L,
- .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_F,
- .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_CAMERA_V,
- .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
- .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_KEYBOARD,
- .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
- .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
- }, {
- .virq = SPEAR300_VIRQ_GPIO1,
- .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
- .status_mask = SPEAR300_GPIO1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = SPEAR300_INT_ENB_MASK_REG,
- .status_reg = SPEAR300_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
- .clear_reg = -1,
- },
-};
-
/* DMAC platform data's slave info */
struct pl08x_channel_data spear300_dma_info[] = {
{
static void __init spear300_dt_init(void)
{
- int ret;
-
pl080_plat_data.slave_channels = spear300_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear300_auxdata_lookup, NULL);
-
- /* shared irq registration */
- shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
- if (shirq_ras1.regs.base) {
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ\n");
- }
}
static const char * const spear300_dt_board_compat[] = {
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
#define SPEAR310_UART3_BASE UL(0xB2100000)
#define SPEAR310_UART4_BASE UL(0xB2180000)
#define SPEAR310_UART5_BASE UL(0xB2200000)
-#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG 0x04
-#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
-
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR310_VIRQ_SMII0,
- .status_mask = SPEAR310_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII1,
- .status_mask = SPEAR310_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII2,
- .status_mask = SPEAR310_SMII2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_SMII3,
- .status_mask = SPEAR310_SMII3_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
- .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
- .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
- .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
- .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_ras2_config[] = {
- {
- .virq = SPEAR310_VIRQ_UART1,
- .status_mask = SPEAR310_UART1_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART2,
- .status_mask = SPEAR310_UART2_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART3,
- .status_mask = SPEAR310_UART3_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART4,
- .status_mask = SPEAR310_UART4_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_UART5,
- .status_mask = SPEAR310_UART5_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras2 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_2,
- .dev_config = shirq_ras2_config,
- .dev_count = ARRAY_SIZE(shirq_ras2_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_ras3_config[] = {
- {
- .virq = SPEAR310_VIRQ_EMI,
- .status_mask = SPEAR310_EMI_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras3 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_3,
- .dev_config = shirq_ras3_config,
- .dev_count = ARRAY_SIZE(shirq_ras3_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
- .clear_reg = -1,
- },
-};
-
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
- {
- .virq = SPEAR310_VIRQ_TDM_HDLC,
- .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_RS485_0,
- .status_mask = SPEAR310_RS485_0_IRQ_MASK,
- }, {
- .virq = SPEAR310_VIRQ_RS485_1,
- .status_mask = SPEAR310_RS485_1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_intrcomm_ras = {
- .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
- .dev_config = shirq_intrcomm_ras_config,
- .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = -1,
- },
-};
/* DMAC platform data's slave info */
struct pl08x_channel_data spear310_dma_info[] = {
static void __init spear310_dt_init(void)
{
- void __iomem *base;
- int ret;
-
pl080_plat_data.slave_channels = spear310_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear310_auxdata_lookup, NULL);
-
- /* shared irq registration */
- base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
- if (base) {
- /* shirq 1 */
- shirq_ras1.regs.base = base;
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ 1\n");
-
- /* shirq 2 */
- shirq_ras2.regs.base = base;
- ret = spear_shirq_register(&shirq_ras2);
- if (ret)
- pr_err("Error registering Shared IRQ 2\n");
-
- /* shirq 3 */
- shirq_ras3.regs.base = base;
- ret = spear_shirq_register(&shirq_ras3);
- if (ret)
- pr_err("Error registering Shared IRQ 3\n");
-
- /* shirq 4 */
- shirq_intrcomm_ras.regs.base = base;
- ret = spear_shirq_register(&shirq_intrcomm_ras);
- if (ret)
- pr_err("Error registering Shared IRQ 4\n");
- }
}
static const char * const spear310_dt_board_compat[] = {
#include <linux/of_platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
-#include <plat/shirq.h>
#include <mach/generic.h>
#include <mach/spear.h>
#define SPEAR320_SSP0_BASE UL(0xA5000000)
#define SPEAR320_SSP1_BASE UL(0xA6000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG 0x04
-#define SPEAR320_INT_CLR_MASK_REG 0x04
-#define SPEAR320_INT_ENB_MASK_REG 0x08
-#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
-
-/* spear3xx shared irq */
-static struct shirq_dev_config shirq_ras1_config[] = {
- {
- .virq = SPEAR320_VIRQ_EMI,
- .status_mask = SPEAR320_EMI_IRQ_MASK,
- .clear_mask = SPEAR320_EMI_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_CLCD,
- .status_mask = SPEAR320_CLCD_IRQ_MASK,
- .clear_mask = SPEAR320_CLCD_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SPP,
- .status_mask = SPEAR320_SPP_IRQ_MASK,
- .clear_mask = SPEAR320_SPP_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras1 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_1,
- .dev_config = shirq_ras1_config,
- .dev_count = ARRAY_SIZE(shirq_ras1_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
-static struct shirq_dev_config shirq_ras3_config[] = {
- {
- .virq = SPEAR320_VIRQ_PLGPIO,
- .enb_mask = SPEAR320_GPIO_IRQ_MASK,
- .status_mask = SPEAR320_GPIO_IRQ_MASK,
- .clear_mask = SPEAR320_GPIO_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2S_PLAY,
- .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2S_REC,
- .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
- .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
- .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_ras3 = {
- .irq = SPEAR3XX_IRQ_GEN_RAS_3,
- .dev_config = shirq_ras3_config,
- .dev_count = ARRAY_SIZE(shirq_ras3_config),
- .regs = {
- .enb_reg = SPEAR320_INT_ENB_MASK_REG,
- .reset_to_enb = 1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
-static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
- {
- .virq = SPEAR320_VIRQ_CANU,
- .status_mask = SPEAR320_CAN_U_IRQ_MASK,
- .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_CANL,
- .status_mask = SPEAR320_CAN_L_IRQ_MASK,
- .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_UART1,
- .status_mask = SPEAR320_UART1_IRQ_MASK,
- .clear_mask = SPEAR320_UART1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_UART2,
- .status_mask = SPEAR320_UART2_IRQ_MASK,
- .clear_mask = SPEAR320_UART2_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SSP1,
- .status_mask = SPEAR320_SSP1_IRQ_MASK,
- .clear_mask = SPEAR320_SSP1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SSP2,
- .status_mask = SPEAR320_SSP2_IRQ_MASK,
- .clear_mask = SPEAR320_SSP2_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_SMII0,
- .status_mask = SPEAR320_SMII0_IRQ_MASK,
- .clear_mask = SPEAR320_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_MII1_SMII1,
- .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
- .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
- .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
- .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
- .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
- .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
- }, {
- .virq = SPEAR320_VIRQ_I2C1,
- .status_mask = SPEAR320_I2C1_IRQ_MASK,
- .clear_mask = SPEAR320_I2C1_IRQ_MASK,
- },
-};
-
-static struct spear_shirq shirq_intrcomm_ras = {
- .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
- .dev_config = shirq_intrcomm_ras_config,
- .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = SPEAR320_INT_CLR_MASK_REG,
- .reset_to_clear = 1,
- },
-};
-
/* DMAC platform data's slave info */
struct pl08x_channel_data spear320_dma_info[] = {
{
static void __init spear320_dt_init(void)
{
- void __iomem *base;
- int ret;
-
pl080_plat_data.slave_channels = spear320_dma_info;
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
of_platform_populate(NULL, of_default_bus_match_table,
spear320_auxdata_lookup, NULL);
-
- /* shared irq registration */
- base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
- if (base) {
- /* shirq 1 */
- shirq_ras1.regs.base = base;
- ret = spear_shirq_register(&shirq_ras1);
- if (ret)
- pr_err("Error registering Shared IRQ 1\n");
-
- /* shirq 3 */
- shirq_ras3.regs.base = base;
- ret = spear_shirq_register(&shirq_ras3);
- if (ret)
- pr_err("Error registering Shared IRQ 3\n");
-
- /* shirq 4 */
- shirq_intrcomm_ras.regs.base = base;
- ret = spear_shirq_register(&shirq_intrcomm_ras);
- if (ret)
- pr_err("Error registering Shared IRQ 4\n");
- }
}
static const char * const spear320_dt_board_compat[] = {
"st,spear320",
"st,spear320-evb",
+ "st,spear320-hmi",
NULL,
};
#include <linux/amba/pl022.h>
#include <linux/amba/pl08x.h>
+#include <linux/irqchip/spear-shirq.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <asm/hardware/pl080.h>
static const struct of_device_id vic_of_match[] __initconst = {
{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+ { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
+ { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
+ { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
{ /* Sentinel */ }
};
# Common support
obj-y := restart.o time.o
-obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX) += pl080.o
obj-$(CONFIG_ARCH_SPEAR6XX) += pl080.o
+++ /dev/null
-/*
- * arch/arm/plat-spear/shirq.c
- *
- * SPEAr platform shared irq layer source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-#include <plat/shirq.h>
-
-struct spear_shirq *shirq;
-static DEFINE_SPINLOCK(lock);
-
-static void shirq_irq_mask(struct irq_data *d)
-{
- struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
- u32 val, id = d->irq - shirq->dev_config[0].virq;
- unsigned long flags;
-
- if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
- return;
-
- spin_lock_irqsave(&lock, flags);
- val = readl(shirq->regs.base + shirq->regs.enb_reg);
- if (shirq->regs.reset_to_enb)
- val |= shirq->dev_config[id].enb_mask;
- else
- val &= ~(shirq->dev_config[id].enb_mask);
- writel(val, shirq->regs.base + shirq->regs.enb_reg);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-static void shirq_irq_unmask(struct irq_data *d)
-{
- struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
- u32 val, id = d->irq - shirq->dev_config[0].virq;
- unsigned long flags;
-
- if ((shirq->regs.enb_reg == -1) || shirq->dev_config[id].enb_mask == -1)
- return;
-
- spin_lock_irqsave(&lock, flags);
- val = readl(shirq->regs.base + shirq->regs.enb_reg);
- if (shirq->regs.reset_to_enb)
- val &= ~(shirq->dev_config[id].enb_mask);
- else
- val |= shirq->dev_config[id].enb_mask;
- writel(val, shirq->regs.base + shirq->regs.enb_reg);
- spin_unlock_irqrestore(&lock, flags);
-}
-
-static struct irq_chip shirq_chip = {
- .name = "spear_shirq",
- .irq_ack = shirq_irq_mask,
- .irq_mask = shirq_irq_mask,
- .irq_unmask = shirq_irq_unmask,
-};
-
-static void shirq_handler(unsigned irq, struct irq_desc *desc)
-{
- u32 i, val, mask;
- struct spear_shirq *shirq = irq_get_handler_data(irq);
-
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
- shirq->regs.status_reg_mask)) {
- for (i = 0; (i < shirq->dev_count) && val; i++) {
- if (!(shirq->dev_config[i].status_mask & val))
- continue;
-
- generic_handle_irq(shirq->dev_config[i].virq);
-
- /* clear interrupt */
- val &= ~shirq->dev_config[i].status_mask;
- if ((shirq->regs.clear_reg == -1) ||
- shirq->dev_config[i].clear_mask == -1)
- continue;
- mask = readl(shirq->regs.base + shirq->regs.clear_reg);
- if (shirq->regs.reset_to_clear)
- mask &= ~shirq->dev_config[i].clear_mask;
- else
- mask |= shirq->dev_config[i].clear_mask;
- writel(mask, shirq->regs.base + shirq->regs.clear_reg);
- }
- }
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-
-int spear_shirq_register(struct spear_shirq *shirq)
-{
- int i;
-
- if (!shirq || !shirq->dev_config || !shirq->regs.base)
- return -EFAULT;
-
- if (!shirq->dev_count)
- return -EINVAL;
-
- irq_set_chained_handler(shirq->irq, shirq_handler);
- for (i = 0; i < shirq->dev_count; i++) {
- irq_set_chip_and_handler(shirq->dev_config[i].virq,
- &shirq_chip, handle_simple_irq);
- set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
- irq_set_chip_data(shirq->dev_config[i].virq, shirq);
- }
-
- irq_set_handler_data(shirq->irq, shirq);
- return 0;
-}
#include <mach/spear.h>
#include "clk.h"
+#define VA_SPEAR1310_RAS_BASE IOMEM(UL(0xFA400000))
/* PLL related registers and bit values */
#define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210)
/* PLL_CFG bit values */
-obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
-obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
-obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
+obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
--- /dev/null
+/*
+ * SPEAr platform shared irq layer source file
+ *
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.linux@gmail.com>
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Shiraz Hashim <shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/spear-shirq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(lock);
+
+/* spear300 shared irq registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+
+static struct spear_shirq spear300_shirq_ras1 = {
+ .irq_nr = 9,
+ .irq_bit_off = 0,
+ .regs = {
+ .enb_reg = SPEAR300_INT_ENB_MASK_REG,
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq *spear300_shirq_blocks[] = {
+ &spear300_shirq_ras1,
+};
+
+/* spear310 shared irq registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG 0x04
+
+static struct spear_shirq spear310_shirq_ras1 = {
+ .irq_nr = 8,
+ .irq_bit_off = 0,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_ras2 = {
+ .irq_nr = 5,
+ .irq_bit_off = 8,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_ras3 = {
+ .irq_nr = 1,
+ .irq_bit_off = 13,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq spear310_shirq_intrcomm_ras = {
+ .irq_nr = 3,
+ .irq_bit_off = 14,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .clear_reg = -1,
+ },
+};
+
+static struct spear_shirq *spear310_shirq_blocks[] = {
+ &spear310_shirq_ras1,
+ &spear310_shirq_ras2,
+ &spear310_shirq_ras3,
+ &spear310_shirq_intrcomm_ras,
+};
+
+/* spear320 shared irq registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+
+static struct spear_shirq spear320_shirq_ras1 = {
+ .irq_nr = 3,
+ .irq_bit_off = 7,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_ras2 = {
+ .irq_nr = 1,
+ .irq_bit_off = 10,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_ras3 = {
+ .irq_nr = 3,
+ .irq_bit_off = 0,
+ .invalid_irq = 1,
+ .regs = {
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
+ .reset_to_enb = 1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq spear320_shirq_intrcomm_ras = {
+ .irq_nr = 11,
+ .irq_bit_off = 11,
+ .regs = {
+ .enb_reg = -1,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
+ .reset_to_clear = 1,
+ },
+};
+
+static struct spear_shirq *spear320_shirq_blocks[] = {
+ &spear320_shirq_ras3,
+ &spear320_shirq_ras1,
+ &spear320_shirq_ras2,
+ &spear320_shirq_intrcomm_ras,
+};
+
+static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
+{
+ struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+ u32 val, offset = d->irq - shirq->irq_base;
+ unsigned long flags;
+
+ if (shirq->regs.enb_reg == -1)
+ return;
+
+ spin_lock_irqsave(&lock, flags);
+ val = readl(shirq->base + shirq->regs.enb_reg);
+
+ if (mask ^ shirq->regs.reset_to_enb)
+ val &= ~(0x1 << shirq->irq_bit_off << offset);
+ else
+ val |= 0x1 << shirq->irq_bit_off << offset;
+
+ writel(val, shirq->base + shirq->regs.enb_reg);
+ spin_unlock_irqrestore(&lock, flags);
+
+}
+
+static void shirq_irq_mask(struct irq_data *d)
+{
+ shirq_irq_mask_unmask(d, 1);
+}
+
+static void shirq_irq_unmask(struct irq_data *d)
+{
+ shirq_irq_mask_unmask(d, 0);
+}
+
+static struct irq_chip shirq_chip = {
+ .name = "spear-shirq",
+ .irq_ack = shirq_irq_mask,
+ .irq_mask = shirq_irq_mask,
+ .irq_unmask = shirq_irq_unmask,
+};
+
+static void shirq_handler(unsigned irq, struct irq_desc *desc)
+{
+ u32 i, j, val, mask, tmp;
+ struct irq_chip *chip;
+ struct spear_shirq *shirq = irq_get_handler_data(irq);
+
+ chip = irq_get_chip(irq);
+ chip->irq_ack(&desc->irq_data);
+
+ mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
+ while ((val = readl(shirq->base + shirq->regs.status_reg) &
+ mask)) {
+
+ val >>= shirq->irq_bit_off;
+ for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
+
+ if (!(j & val))
+ continue;
+
+ generic_handle_irq(shirq->irq_base + i);
+
+ /* clear interrupt */
+ if (shirq->regs.clear_reg == -1)
+ continue;
+
+ tmp = readl(shirq->base + shirq->regs.clear_reg);
+ if (shirq->regs.reset_to_clear)
+ tmp &= ~(j << shirq->irq_bit_off);
+ else
+ tmp |= (j << shirq->irq_bit_off);
+ writel(tmp, shirq->base + shirq->regs.clear_reg);
+ }
+ }
+ chip->irq_unmask(&desc->irq_data);
+}
+
+static void __init spear_shirq_register(struct spear_shirq *shirq)
+{
+ int i;
+
+ if (shirq->invalid_irq)
+ return;
+
+ irq_set_chained_handler(shirq->irq, shirq_handler);
+ for (i = 0; i < shirq->irq_nr; i++) {
+ irq_set_chip_and_handler(shirq->irq_base + i,
+ &shirq_chip, handle_simple_irq);
+ set_irq_flags(shirq->irq_base + i, IRQF_VALID);
+ irq_set_chip_data(shirq->irq_base + i, shirq);
+ }
+
+ irq_set_handler_data(shirq->irq, shirq);
+}
+
+static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
+ struct device_node *np)
+{
+ int i, irq_base, hwirq = 0, irq_nr = 0;
+ static struct irq_domain *shirq_domain;
+ void __iomem *base;
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ pr_err("%s: failed to map shirq registers\n", __func__);
+ return -ENXIO;
+ }
+
+ for (i = 0; i < block_nr; i++)
+ irq_nr += shirq_blocks[i]->irq_nr;
+
+ irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
+ if (IS_ERR_VALUE(irq_base)) {
+ pr_err("%s: irq desc alloc failed\n", __func__);
+ goto err_unmap;
+ }
+
+ shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
+ &irq_domain_simple_ops, NULL);
+ if (WARN_ON(!shirq_domain)) {
+ pr_warn("%s: irq domain init failed\n", __func__);
+ goto err_free_desc;
+ }
+
+ for (i = 0; i < block_nr; i++) {
+ shirq_blocks[i]->base = base;
+ shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
+ hwirq);
+ shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
+
+ spear_shirq_register(shirq_blocks[i]);
+ hwirq += shirq_blocks[i]->irq_nr;
+ }
+
+ return 0;
+
+err_free_desc:
+ irq_free_descs(irq_base, irq_nr);
+err_unmap:
+ iounmap(base);
+ return -ENXIO;
+}
+
+int __init spear300_shirq_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return shirq_init(spear300_shirq_blocks,
+ ARRAY_SIZE(spear300_shirq_blocks), np);
+}
+
+int __init spear310_shirq_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return shirq_init(spear310_shirq_blocks,
+ ARRAY_SIZE(spear310_shirq_blocks), np);
+}
+
+int __init spear320_shirq_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return shirq_init(spear320_shirq_blocks,
+ ARRAY_SIZE(spear320_shirq_blocks), np);
+}
/*
- * arch/arm/plat-spear/include/plat/shirq.h
- *
* SPEAr platform shared irq layer header file
*
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* warranty of any kind, whether express or implied.
*/
-#ifndef __PLAT_SHIRQ_H
-#define __PLAT_SHIRQ_H
+#ifndef __SPEAR_SHIRQ_H
+#define __SPEAR_SHIRQ_H
#include <linux/irq.h>
#include <linux/types.h>
/*
- * struct shirq_dev_config: shared irq device configuration
- *
- * virq: virtual irq number of device
- * enb_mask: enable mask of device
- * status_mask: status mask of device
- * clear_mask: clear mask of device
- */
-struct shirq_dev_config {
- u32 virq;
- u32 enb_mask;
- u32 status_mask;
- u32 clear_mask;
-};
-
-/*
* struct shirq_regs: shared irq register configuration
*
- * base: base address of shared irq register
* enb_reg: enable register offset
* reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
* status_reg: status register offset
* reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
*/
struct shirq_regs {
- void __iomem *base;
u32 enb_reg;
u32 reset_to_enb;
u32 status_reg;
- u32 status_reg_mask;
u32 clear_reg;
u32 reset_to_clear;
};
* struct spear_shirq: shared irq structure
*
* irq: hardware irq number
- * dev_config: array of device config structures which are using "irq" line
- * dev_count: size of dev_config array
+ * irq_base: base irq in linux domain
+ * irq_nr: no. of shared interrupts in a particular block
+ * irq_bit_off: starting bit offset in the status register
+ * invalid_irq: irq group is currently disabled
+ * base: base address of shared irq register
* regs: register configuration for shared irq block
*/
struct spear_shirq {
u32 irq;
- struct shirq_dev_config *dev_config;
- u32 dev_count;
+ u32 irq_base;
+ u32 irq_nr;
+ u32 irq_bit_off;
+ int invalid_irq;
+ void __iomem *base;
struct shirq_regs regs;
};
-int spear_shirq_register(struct spear_shirq *shirq);
+int __init spear300_shirq_of_init(struct device_node *np,
+ struct device_node *parent);
+int __init spear310_shirq_of_init(struct device_node *np,
+ struct device_node *parent);
+int __init spear320_shirq_of_init(struct device_node *np,
+ struct device_node *parent);
-#endif /* __PLAT_SHIRQ_H */
+#endif /* __SPEAR_SHIRQ_H */
projects / profile / ivi / kernel-x86-ivi.git / commitdiff