clk: add sys1_pll for g12b

PD#165090: add sys1_pll for g12b

Change-Id: Icc1be3df1ca9ba2863ce49e0acf0be872e2dd411
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c
index c49aa5b..86a4a40 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.c
+++ b/drivers/amlogic/clk/g12a/g12a.c
@@ -103,6 +103,34 @@ static struct meson_clk_pll g12a_sys_pll = {
        },
 };
 
+static struct meson_clk_pll g12b_sys1_pll = {
+       .m = {
+               .reg_off = HHI_SYS1_PLL_CNTL0,
+               .shift   = 0,
+               .width   = 9,
+       },
+       .n = {
+               .reg_off = HHI_SYS1_PLL_CNTL0,
+               .shift   = 10,
+               .width   = 5,
+       },
+       .od = {
+               .reg_off = HHI_SYS1_PLL_CNTL0,
+               .shift   = 16,
+               .width   = 3,
+       },
+       .rate_table = g12a_pll_rate_table,
+       .rate_count = ARRAY_SIZE(g12a_pll_rate_table),
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "sys1_pll",
+               .ops = &meson_g12a_pll_ops,
+               .parent_names = (const char *[]){ "xtal" },
+               .num_parents = 1,
+               .flags = CLK_GET_RATE_NOCACHE,
+       },
+};
+
 static struct meson_clk_pll g12a_gp0_pll = {
        .m = {
                .reg_off = HHI_GP0_PLL_CNTL0,
@@ -752,6 +780,7 @@ static MESON_GATE(g12a_ao_i2c, HHI_GCLK_AO, 4);
 
 static struct clk_hw *g12a_clk_hws[] = {
        [CLKID_SYS_PLL]         = &g12a_sys_pll.hw,
+       [CLKID_SYS1_PLL]         = &g12b_sys1_pll.hw,
        [CLKID_FIXED_PLL]       = &g12a_fixed_pll.hw,
        [CLKID_GP0_PLL]         = &g12a_gp0_pll.hw,
        [CLKID_HIFI_PLL]        = &g12a_hifi_pll.hw,
@@ -861,6 +890,7 @@ static struct clk_hw *g12a_clk_hws[] = {
 static struct meson_clk_pll *const g12a_clk_plls[] = {
        &g12a_fixed_pll,
        &g12a_sys_pll,
+       &g12b_sys1_pll,
        &g12a_gp0_pll,
        &g12a_hifi_pll,
        &g12a_pcie_pll,

diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h
index 99b50cf..2e4fa81 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.h
+++ b/drivers/amlogic/clk/g12a/g12a.h
@@ -105,6 +105,16 @@
 #define HHI_SYS_PLL_CNTL5              0x308 /* 0xc2 offset in data sheet */
 #define HHI_SYS_PLL_CNTL6              0x30c /* 0xc3 offset in data sheet */
 
+/* For G12B only */
+#define HHI_SYS1_PLL_CNTL0             0x380 /* 0xe0 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL1             0x384 /* 0xe1 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL2             0x388 /* 0xe2 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL3             0x38c /* 0xe3 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL4             0x390 /* 0xe4 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL5             0x394 /* 0xe5 offset in data sheet */
+#define HHI_SYS1_PLL_CNTL6             0x398 /* 0xe6 offset in data sheet */
+/*****************/
+
 #define HHI_SPICC_CLK_CNTL      0x3dc /* 0xf7 offset in data sheet */
 /* AO registers*/
 #define AO_RTI_PWR_CNTL_REG0 0x10 /* 0x4 offset in data sheet */

diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h
index d4a0b89..1440a3b 100644 (file)
--- a/include/dt-bindings/clock/amlogic,g12a-clkc.h
+++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h
@@ -257,7 +257,11 @@
 #define CLKID_SPICC1_COMP        (CLKID_MISC_BASE + 7)
 #define CLKID_TS_COMP           (CLKID_MISC_BASE + 8)
 
-#define CLKID_AO_BASE           (CLKID_MISC_BASE + 9)
+/*G12B clk*/
+#define CLKID_G12B_ADD_BASE     (CLKID_MISC_BASE + 9)
+#define CLKID_SYS1_PLL          (CLKID_G12B_ADD_BASE + 0)
+
+#define CLKID_AO_BASE           (CLKID_G12B_ADD_BASE + 1)
 #define CLKID_AO_CLK81          (CLKID_AO_BASE + 0)
 #define CLKID_SARADC_MUX        (CLKID_AO_BASE + 1)
 #define CLKID_SARADC_DIV        (CLKID_AO_BASE + 2)