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drm/amd/amdgpu: enable uvd&vce clock gating for Fiji.
author
Eric Huang
<JinHuiEric.Huang@amd.com>
Tue, 24 Nov 2015 15:53:27 +0000
(10:53 -0500)
committer
Alex Deucher
<alexander.deucher@amd.com>
Mon, 21 Dec 2015 21:42:46 +0000
(16:42 -0500)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
drivers/gpu/drm/amd/amdgpu/vi.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/vi.c
b/drivers/gpu/drm/amd/amdgpu/vi.c
index
67845ee
..
652e766
100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/
drivers/gpu/drm/amd/amdgpu/vi.c
@@
-1442,7
+1442,8
@@
static int vi_common_early_init(void *handle)
break;
case CHIP_FIJI:
adev->has_uvd = true;
- adev->cg_flags = 0;
+ adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
+ AMDGPU_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;