i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields

Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fddb373..ed2c913 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -43,9 +43,9 @@ void enable_usboh3_clk(unsigned char enable)
 
        reg = __raw_readl(&imx_ccm->CCGR6);
        if (enable)
-               reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+               reg |= MXC_CCM_CCGR6_USBOH3_MASK;
        else
-               reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+               reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
        __raw_writel(reg, &imx_ccm->CCGR6);
 
 }
@@ -59,7 +59,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 
        if (i2c_num > 2)
                return -EINVAL;
-       mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
+
+       mask = MXC_CCM_CCGR_CG_MASK
+               << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
        reg = __raw_readl(&imx_ccm->CCGR2);
        if (enable)
                reg |= mask;
@@ -321,7 +323,7 @@ int enable_sata_clock(void)
 
        /* Enable sata clock */
        reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
-       reg |= MXC_CCM_CCGR5_CG2_MASK;
+       reg |= MXC_CCM_CCGR5_SATA_MASK;
        writel(reg, &imx_ccm->CCGR5);
 
        /* Enable PLLs */

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 0e605c2..59b17b9 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -395,185 +395,185 @@ struct mxc_ccm_reg {
 /* Define the bits in registers CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           3
 
-#define MXC_CCM_CCGR0_CG15_OFFSET                      30
-#define MXC_CCM_CCGR0_CG15_MASK                        (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET                      28
-#define MXC_CCM_CCGR0_CG14_MASK                        (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET                      26
-#define MXC_CCM_CCGR0_CG13_MASK                        (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET                      24
-#define MXC_CCM_CCGR0_CG12_MASK                        (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET                      22
-#define MXC_CCM_CCGR0_CG11_MASK                        (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET                      20
-#define MXC_CCM_CCGR0_CG10_MASK                        (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET                       18
-#define MXC_CCM_CCGR0_CG9_MASK                 (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET                       16
-#define MXC_CCM_CCGR0_CG8_MASK                 (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET                       14
-#define MXC_CCM_CCGR0_CG6_OFFSET                       12
-#define MXC_CCM_CCGR0_CG5_OFFSET                       10
-#define MXC_CCM_CCGR0_CG5_MASK                 (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET                       8
-#define MXC_CCM_CCGR0_CG4_MASK                 (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET                       6
-#define MXC_CCM_CCGR0_CG3_MASK                 (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET                       4
-#define MXC_CCM_CCGR0_CG2_MASK                 (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET                       2
-#define MXC_CCM_CCGR0_CG1_MASK                 (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET                       0
-#define MXC_CCM_CCGR0_CG0_MASK                         3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET                      30
-#define MXC_CCM_CCGR1_CG14_OFFSET                      28
-#define MXC_CCM_CCGR1_CG13_OFFSET                      26
-#define MXC_CCM_CCGR1_CG12_OFFSET                      24
-#define MXC_CCM_CCGR1_CG11_OFFSET                      22
-#define MXC_CCM_CCGR1_CG10_OFFSET                      20
-#define MXC_CCM_CCGR1_CG9_OFFSET                       18
-#define MXC_CCM_CCGR1_CG8_OFFSET                       16
-#define MXC_CCM_CCGR1_CG7_OFFSET                       14
-#define MXC_CCM_CCGR1_CG6_OFFSET                       12
-#define MXC_CCM_CCGR1_CG5_OFFSET                       10
-#define MXC_CCM_CCGR1_CG4_OFFSET                       8
-#define MXC_CCM_CCGR1_CG3_OFFSET                       6
-#define MXC_CCM_CCGR1_CG2_OFFSET                       4
-#define MXC_CCM_CCGR1_CG1_OFFSET                       2
-#define MXC_CCM_CCGR1_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET                      30
-#define MXC_CCM_CCGR2_CG14_OFFSET                      28
-#define MXC_CCM_CCGR2_CG13_OFFSET                      26
-#define MXC_CCM_CCGR2_CG12_OFFSET                      24
-#define MXC_CCM_CCGR2_CG11_OFFSET                      22
-#define MXC_CCM_CCGR2_CG10_OFFSET                      20
-#define MXC_CCM_CCGR2_CG9_OFFSET                       18
-#define MXC_CCM_CCGR2_CG8_OFFSET                       16
-#define MXC_CCM_CCGR2_CG7_OFFSET                       14
-#define MXC_CCM_CCGR2_CG6_OFFSET                       12
-#define MXC_CCM_CCGR2_CG5_OFFSET                       10
-#define MXC_CCM_CCGR2_CG4_OFFSET                       8
-#define MXC_CCM_CCGR2_CG3_OFFSET                       6
-#define MXC_CCM_CCGR2_CG2_OFFSET                       4
-#define MXC_CCM_CCGR2_CG1_OFFSET                       2
-#define MXC_CCM_CCGR2_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET                      30
-#define MXC_CCM_CCGR3_CG14_OFFSET                      28
-#define MXC_CCM_CCGR3_CG13_OFFSET                      26
-#define MXC_CCM_CCGR3_CG12_OFFSET                      24
-#define MXC_CCM_CCGR3_CG11_OFFSET                      22
-#define MXC_CCM_CCGR3_CG10_OFFSET                      20
-#define MXC_CCM_CCGR3_CG9_OFFSET                       18
-#define MXC_CCM_CCGR3_CG8_OFFSET                       16
-#define MXC_CCM_CCGR3_CG7_OFFSET                       14
-#define MXC_CCM_CCGR3_CG6_OFFSET                       12
-#define MXC_CCM_CCGR3_CG5_OFFSET                       10
-#define MXC_CCM_CCGR3_CG4_OFFSET                       8
-#define MXC_CCM_CCGR3_CG3_OFFSET                       6
-#define MXC_CCM_CCGR3_CG2_OFFSET                       4
-#define MXC_CCM_CCGR3_CG1_OFFSET                       2
-#define MXC_CCM_CCGR3_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET                      30
-#define MXC_CCM_CCGR4_CG14_OFFSET                      28
-#define MXC_CCM_CCGR4_CG13_OFFSET                      26
-#define MXC_CCM_CCGR4_CG12_OFFSET                      24
-#define MXC_CCM_CCGR4_CG11_OFFSET                      22
-#define MXC_CCM_CCGR4_CG10_OFFSET                      20
-#define MXC_CCM_CCGR4_CG9_OFFSET                       18
-#define MXC_CCM_CCGR4_CG8_OFFSET                       16
-#define MXC_CCM_CCGR4_CG7_OFFSET                       14
-#define MXC_CCM_CCGR4_CG6_OFFSET                       12
-#define MXC_CCM_CCGR4_CG5_OFFSET                       10
-#define MXC_CCM_CCGR4_CG4_OFFSET                       8
-#define MXC_CCM_CCGR4_CG3_OFFSET                       6
-#define MXC_CCM_CCGR4_CG2_OFFSET                       4
-#define MXC_CCM_CCGR4_CG1_OFFSET                       2
-#define MXC_CCM_CCGR4_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET                      30
-#define MXC_CCM_CCGR5_CG14_OFFSET                      28
-#define MXC_CCM_CCGR5_CG14_MASK                        (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET                      26
-#define MXC_CCM_CCGR5_CG13_MASK                        (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET                      24
-#define MXC_CCM_CCGR5_CG12_MASK                        (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET                      22
-#define MXC_CCM_CCGR5_CG11_MASK                        (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET                      20
-#define MXC_CCM_CCGR5_CG10_MASK                        (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET                       18
-#define MXC_CCM_CCGR5_CG9_MASK                 (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET                       16
-#define MXC_CCM_CCGR5_CG8_MASK                 (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET                       14
-#define MXC_CCM_CCGR5_CG7_MASK                 (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_OFFSET                       12
-#define MXC_CCM_CCGR5_CG6_MASK                 (0x3 << 12)
-#define MXC_CCM_CCGR5_CG5_OFFSET                       10
-#define MXC_CCM_CCGR5_CG4_OFFSET                       8
-#define MXC_CCM_CCGR5_CG3_OFFSET                       6
-#define MXC_CCM_CCGR5_CG2_OFFSET                       4
-#define MXC_CCM_CCGR5_CG2_MASK                 (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET                       2
-#define MXC_CCM_CCGR5_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR6_CG15_OFFSET                      30
-#define MXC_CCM_CCGR6_CG14_OFFSET                      28
-#define MXC_CCM_CCGR6_CG14_MASK                        (0x3 << 28)
-#define MXC_CCM_CCGR6_CG13_OFFSET                      26
-#define MXC_CCM_CCGR6_CG13_MASK                        (0x3 << 26)
-#define MXC_CCM_CCGR6_CG12_OFFSET                      24
-#define MXC_CCM_CCGR6_CG12_MASK                        (0x3 << 24)
-#define MXC_CCM_CCGR6_CG11_OFFSET                      22
-#define MXC_CCM_CCGR6_CG11_MASK                        (0x3 << 22)
-#define MXC_CCM_CCGR6_CG10_OFFSET                      20
-#define MXC_CCM_CCGR6_CG10_MASK                        (0x3 << 20)
-#define MXC_CCM_CCGR6_CG9_OFFSET                       18
-#define MXC_CCM_CCGR6_CG9_MASK                 (0x3 << 18)
-#define MXC_CCM_CCGR6_CG8_OFFSET                       16
-#define MXC_CCM_CCGR6_CG8_MASK                 (0x3 << 16)
-#define MXC_CCM_CCGR6_CG7_OFFSET                       14
-#define MXC_CCM_CCGR6_CG7_MASK                 (0x3 << 14)
-#define MXC_CCM_CCGR6_CG6_OFFSET                       12
-#define MXC_CCM_CCGR6_CG6_MASK                 (0x3 << 12)
-#define MXC_CCM_CCGR6_CG5_OFFSET                       10
-#define MXC_CCM_CCGR6_CG4_OFFSET                       8
-#define MXC_CCM_CCGR6_CG3_OFFSET                       6
-#define MXC_CCM_CCGR6_CG2_OFFSET                       4
-#define MXC_CCM_CCGR6_CG2_MASK                 (0x3 << 4)
-#define MXC_CCM_CCGR6_CG1_OFFSET                       2
-#define MXC_CCM_CCGR6_CG0_OFFSET                       0
-
-#define MXC_CCM_CCGR7_CG15_OFFSET                      30
-#define MXC_CCM_CCGR7_CG14_OFFSET                      28
-#define MXC_CCM_CCGR7_CG14_MASK                        (0x3 << 28)
-#define MXC_CCM_CCGR7_CG13_OFFSET                      26
-#define MXC_CCM_CCGR7_CG13_MASK                        (0x3 << 26)
-#define MXC_CCM_CCGR7_CG12_OFFSET                      24
-#define MXC_CCM_CCGR7_CG12_MASK                        (0x3 << 24)
-#define MXC_CCM_CCGR7_CG11_OFFSET                      22
-#define MXC_CCM_CCGR7_CG11_MASK                        (0x3 << 22)
-#define MXC_CCM_CCGR7_CG10_OFFSET                      20
-#define MXC_CCM_CCGR7_CG10_MASK                        (0x3 << 20)
-#define MXC_CCM_CCGR7_CG9_OFFSET                       18
-#define MXC_CCM_CCGR7_CG9_MASK                 (0x3 << 18)
-#define MXC_CCM_CCGR7_CG8_OFFSET                       16
-#define MXC_CCM_CCGR7_CG8_MASK                 (0x3 << 16)
-#define MXC_CCM_CCGR7_CG7_OFFSET                       14
-#define MXC_CCM_CCGR7_CG7_MASK                 (0x3 << 14)
-#define MXC_CCM_CCGR7_CG6_OFFSET                       12
-#define MXC_CCM_CCGR7_CG6_MASK                 (0x3 << 12)
-#define MXC_CCM_CCGR7_CG5_OFFSET                       10
-#define MXC_CCM_CCGR7_CG4_OFFSET                       8
-#define MXC_CCM_CCGR7_CG3_OFFSET                       6
-#define MXC_CCM_CCGR7_CG2_OFFSET                       4
-#define MXC_CCM_CCGR7_CG2_MASK                 (0x3 << 4)
-#define MXC_CCM_CCGR7_CG1_OFFSET                       2
-#define MXC_CCM_CCGR7_CG0_OFFSET                       0
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET                  0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK                    (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET                  2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK                    (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET              4
+#define MXC_CCM_CCGR0_AMASK                            (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_ASRC_OFFSET                      6
+#define MXC_CCM_CCGR0_ASRC_MASK                                (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET           8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK             (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET         10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK           (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET          12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK            (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET                      14
+#define MXC_CCM_CCGR0_CAN1_MASK                                (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET               16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK                 (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET                      18
+#define MXC_CCM_CCGR0_CAN2_MASK                                (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET               20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK                 (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET           22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK             (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET                     24
+#define MXC_CCM_CCGR0_DCIC1_MASK                       (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET                     26
+#define MXC_CCM_CCGR0_DCIC2_MASK                       (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_OFFSET                      28
+#define MXC_CCM_CCGR0_DTCP_MASK                                (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET                   0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET                   2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET                   4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET                   6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET                    12
+#define MXC_CCM_CCGR1_EPIT1S_MASK                      (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET                    14
+#define MXC_CCM_CCGR1_EPIT2S_MASK                      (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET                     16
+#define MXC_CCM_CCGR1_ESAIS_MASK                       (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET                   20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                        22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_OFFSET                     24
+#define MXC_CCM_CCGR1_GPU2D_MASK                       (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_OFFSET                     26
+#define MXC_CCM_CCGR1_GPU3D_MASK                       (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET               6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK            (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET                    16
+#define MXC_CCM_CCGR2_IPMUX1_MASK                      (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET                    18
+#define MXC_CCM_CCGR2_IPMUX2_MASK                      (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET                    20
+#define MXC_CCM_CCGR2_IPMUX3_MASK                      (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET  24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK    (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET        26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET                          0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK                            (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET                      2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK                                (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET                      4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK                                (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET                          6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK                            (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET                      8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK                                (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET                      10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET                           14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK                             (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET                     16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK                       (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MLB_OFFSET                               18
+#define MXC_CCM_CCGR3_MLB_MASK                                 (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET       22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET              24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK                        (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET              26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
+#define MXC_CCM_CCGR3_OCRAM_MASK                               (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET                              0
+#define MXC_CCM_CCGR4_PCIE_MASK                                        (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET              8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK                        (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET                        12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK                  (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET     14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK       (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET                              16
+#define MXC_CCM_CCGR4_PWM1_MASK                                        (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET                              18
+#define MXC_CCM_CCGR4_PWM2_MASK                                        (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET                              20
+#define MXC_CCM_CCGR4_PWM3_MASK                                        (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET                              22
+#define MXC_CCM_CCGR4_PWM4_MASK                                        (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET           24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK             (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET      26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK                (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET  28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK    (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET          30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK            (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET                       0
+#define MXC_CCM_CCGR5_ROM_MASK                         (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET                      4
+#define MXC_CCM_CCGR5_SATA_MASK                                (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_OFFSET                      6
+#define MXC_CCM_CCGR5_SDMA_MASK                                (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET                      12
+#define MXC_CCM_CCGR5_SPBA_MASK                                (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET                     14
+#define MXC_CCM_CCGR5_SPDIF_MASK                       (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET                      18
+#define MXC_CCM_CCGR5_SSI1_MASK                                (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET                      20
+#define MXC_CCM_CCGR5_SSI2_MASK                                (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET                      22
+#define MXC_CCM_CCGR5_SSI3_MASK                                (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET                      24
+#define MXC_CCM_CCGR5_UART_MASK                                (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET            0
+#define MXC_CCM_CCGR6_USBOH3_MASK              (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET            2
+#define MXC_CCM_CCGR6_USDHC1_MASK              (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET            4
+#define MXC_CCM_CCGR6_USDHC2_MASK              (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET            6
+#define MXC_CCM_CCGR6_USDHC3_MASK              (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET            8
+#define MXC_CCM_CCGR6_USDHC4_MASK              (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET          10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK            (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET         12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK           (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
 #define BP_ANADIG_PLL_SYS_RSVD0      20
 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 2020da9..cc8f881 100644 (file)
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -163,13 +163,13 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
 static int clk_ipu_enable(struct clk *clk)
 {
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        u32 reg;
 
        reg = __raw_readl(clk->enable_reg);
        reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
        __raw_writel(reg, clk->enable_reg);
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        /* Handshake with IPU when certain clock rates are changed. */
        reg = __raw_readl(&mxc_ccm->ccdr);
        reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
@@ -185,13 +185,13 @@ static int clk_ipu_enable(struct clk *clk)
 
 static void clk_ipu_disable(struct clk *clk)
 {
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        u32 reg;
 
        reg = __raw_readl(clk->enable_reg);
        reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
        __raw_writel(reg, clk->enable_reg);
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        /*
         * No handshake with IPU whe dividers are changed
         * as its not enabled.
@@ -211,9 +211,15 @@ static void clk_ipu_disable(struct clk *clk)
 static struct clk ipu_clk = {
        .name = "ipu_clk",
        .rate = CONFIG_IPUV3_CLK,
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR5)),
        .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+#else
+       .enable_reg = (u32 *)(CCM_BASE_ADDR +
+               offsetof(struct mxc_ccm_reg, CCGR3)),
+       .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
+#endif
        .enable = clk_ipu_enable,
        .disable = clk_ipu_disable,
        .usecount = 0,