drm/i915/adl_p: Implement Wa_22012358565

Implement Wa_22012358565 to avoid underrun with 32bpp cursor
in some high bandwidth scenarios. The implementation calls for
overriding the arbitration slots for the planes.

v2: Fix adlp_plane_ctl_arb_slots() return type

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210526173600.27708-2-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2ab389b..966e020 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -383,6 +383,10 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
        if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
                cntl |= MCURSOR_ROTATE_180;
 
+       /* Wa_22012358565:adlp */
+       if (DISPLAY_VER(dev_priv) == 13)
+               cntl |= MCURSOR_ARB_SLOTS(1);
+
        return cntl;
 }
 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 55c6a34..a363664 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -975,6 +975,11 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
                /* FIXME: assert CPU port conditions for SNB+ */
        }
 
+       /* Wa_22012358565:adlp */
+       if (DISPLAY_VER(dev_priv) == 13)
+               intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
+                            0, PIPE_ARB_USE_PROG_SLOTS);
+
        reg = PIPECONF(cpu_transcoder);
        val = intel_de_read(dev_priv, reg);
        if (val & PIPECONF_ENABLE) {

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 59e032f..92a4fd5 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -850,6 +850,29 @@ static u32 cnl_plane_ctl_flip(unsigned int reflect)
        return 0;
 }
 
+static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
+{
+       const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+       if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+               switch (fb->format->cpp[0]) {
+               case 2:
+                       return PLANE_CTL_ARB_SLOTS(1);
+               default:
+                       return PLANE_CTL_ARB_SLOTS(0);
+               }
+       } else {
+               switch (fb->format->cpp[0]) {
+               case 8:
+                       return PLANE_CTL_ARB_SLOTS(3);
+               case 4:
+                       return PLANE_CTL_ARB_SLOTS(1);
+               default:
+                       return PLANE_CTL_ARB_SLOTS(0);
+               }
+       }
+}
+
 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
@@ -903,6 +926,10 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
        else if (key->flags & I915_SET_COLORKEY_SOURCE)
                plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 
+       /* Wa_22012358565:adlp */
+       if (DISPLAY_VER(dev_priv) == 13)
+               plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
+
        return plane_ctl;
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd522e4..d7302cc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6140,6 +6140,10 @@ enum {
 #define  _PIPEBGCMAX           0x71010
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
+#define _PIPE_ARB_CTL_A                        0x70028 /* icl+ */
+#define PIPE_ARB_CTL(pipe)             _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
+#define   PIPE_ARB_USE_PROG_SLOTS      REG_BIT(13)
+
 #define _PIPE_MISC_A                   0x70030
 #define _PIPE_MISC_B                   0x71030
 #define   PIPEMISC_YUV420_ENABLE       (1 << 27) /* glk+ */
@@ -6604,6 +6608,8 @@ enum {
 #define   MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX)
 #define   MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX)
 #define   MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX)
+#define   MCURSOR_ARB_SLOTS_MASK       REG_GENMASK(30, 28) /* icl+ */
+#define   MCURSOR_ARB_SLOTS(x)         REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
 #define   MCURSOR_PIPE_SELECT_MASK     (0x3 << 28)
 #define   MCURSOR_PIPE_SELECT_SHIFT    28
 #define   MCURSOR_PIPE_SELECT(pipe)    ((pipe) << 28)
@@ -7055,6 +7061,8 @@ enum {
 #define _PLANE_CTL_2_A                         0x70280
 #define _PLANE_CTL_3_A                         0x70380
 #define   PLANE_CTL_ENABLE                     (1 << 31)
+#define   PLANE_CTL_ARB_SLOTS_MASK             REG_GENMASK(30, 28) /* icl+ */
+#define   PLANE_CTL_ARB_SLOTS(x)               REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
 #define   PLANE_CTL_PIPE_GAMMA_ENABLE          (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE       (1 << 28)
 /*