Correct the register region in VME kernel

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/shaders/vme/inter_frame.asm b/src/shaders/vme/inter_frame.asm
index aba5bc7..e644a19 100644 (file)
--- a/src/shaders/vme/inter_frame.asm
+++ b/src/shaders/vme/inter_frame.asm
@@ -25,10 +25,10 @@ mov  (16) tmp_reg3.0<1>:UD      0x0:UD {align1};
 
 shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* Source =  (x, y) * 16 */
         
-#ifdef DEV_SNB        
+#ifdef DEV_SNB
 shl  (2) vme_m0.0<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    
-add  (1) vme_m0.0<1>:W          vme_m0.0<2,2,1>:W -16:W {align1};              /* Reference = (x-16,y-12)-(x+32,y+24) */
-add  (1) vme_m0.2<1>:W          vme_m0.2<2,2,1>:W -12:W {align1};
+add  (1) vme_m0.0<1>:W          vme_m0.0<0,1,0>:W -16:W {align1};              /* Reference = (x-16,y-12)-(x+32,y+24) */
+add  (1) vme_m0.2<1>:W          vme_m0.2<0,1,0>:W -12:W {align1};
 #else
 mov  (1) vme_m0.0<1>:W          -16:W {align1} ;                /* Reference = (x-16,y-12)-(x+32,y+24) */
 mov  (1) vme_m0.2<1>:W          -12:W {align1} ;
@@ -88,15 +88,15 @@ mov  (8) msg_reg0.0<1>:UD       obw_m0.0<8,8,1>:UD {align1};
 
 #ifdef DEV_SNB        
 mov  (2) obw_m1.0<1>:UW         vme_wb1.0<2,2,1>:UB  {align1};
-add  (1) obw_m1.0<1>:W          obw_m1.0<2,2,1>:W -64:W {align1};
-add  (1) obw_m1.2<1>:W          obw_m1.2<2,2,1>:W -48:W {align1}; 
+add  (1) obw_m1.0<1>:W          obw_m1.0<0,1,0>:W -64:W {align1};
+add  (1) obw_m1.2<1>:W          obw_m1.2<0,1,0>:W -48:W {align1}; 
 #else
 mov  (2) obw_m1.0<1>:UW         vme_wb1.0<2,2,1>:B  {align1};        
 #endif       
         
-mov  (8) msg_reg1.0<1>:UD       obw_m1.0<8,8,0>:UD   {align1};
+mov  (8) msg_reg1.0<1>:UD       obw_m1.0<0,1,0>:UD   {align1};
 
-mov  (8) msg_reg2.0<1>:UD       obw_m1.0<8,8,0>:UD   {align1};
+mov  (8) msg_reg2.0<1>:UD       obw_m1.0<0,1,0>:UD   {align1};
 
 /* bind index 3, write 8 oword, msg type: 8(OWord Block Write) */
 send (16)

diff --git a/src/shaders/vme/inter_frame.g6b b/src/shaders/vme/inter_frame.g6b
index 015d126..e554fb0 100644 (file)
--- a/src/shaders/vme/inter_frame.g6b
+++ b/src/shaders/vme/inter_frame.g6b
@@ -3,8 +3,8 @@
    { 0x00800001, 0x24600061, 0x00000000, 0x00000000 },
    { 0x00200009, 0x24482e29, 0x004500a0, 0x00040004 },
    { 0x00200009, 0x24402e29, 0x004500a0, 0x00040004 },
-   { 0x00000040, 0x24403dad, 0x00450440, 0xfff0fff0 },
-   { 0x00000040, 0x24423dad, 0x00450442, 0xfff4fff4 },
+   { 0x00000040, 0x24403dad, 0x00000440, 0xfff0fff0 },
+   { 0x00000040, 0x24423dad, 0x00000442, 0xfff4fff4 },
    { 0x00000001, 0x244c0061, 0x00000000, 0x70203100 },
    { 0x00000001, 0x24540231, 0x00000014, 0x00000000 },
    { 0x00000001, 0x24560169, 0x00000000, 0x28302830 },
@@ -23,10 +23,10 @@
    { 0x08600031, 0x21801cdd, 0x00000000, 0x08482000 },
    { 0x00600001, 0x20000022, 0x008d0480, 0x00000000 },
    { 0x00200001, 0x24a00229, 0x004501a0, 0x00000000 },
-   { 0x00000040, 0x24a03dad, 0x004504a0, 0xffc0ffc0 },
-   { 0x00000040, 0x24a23dad, 0x004504a2, 0xffd0ffd0 },
-   { 0x00600001, 0x20200022, 0x008c04a0, 0x00000000 },
-   { 0x00600001, 0x20400022, 0x008c04a0, 0x00000000 },
+   { 0x00000040, 0x24a03dad, 0x000004a0, 0xffc0ffc0 },
+   { 0x00000040, 0x24a23dad, 0x000004a2, 0xffd0ffd0 },
+   { 0x00600001, 0x20200022, 0x000004a0, 0x00000000 },
+   { 0x00600001, 0x20400022, 0x000004a0, 0x00000000 },
    { 0x05800031, 0x22001cdd, 0x00000000, 0x0a1b0403 },
    { 0x00000040, 0x20080c22, 0x00000488, 0x00000008 },
    { 0x00000001, 0x20200022, 0x00000180, 0x00000000 },

diff --git a/src/shaders/vme/inter_frame.g7b b/src/shaders/vme/inter_frame.g7b
index 0205c0f..766be0f 100644 (file)
--- a/src/shaders/vme/inter_frame.g7b
+++ b/src/shaders/vme/inter_frame.g7b
@@ -22,8 +22,8 @@
    { 0x08600031, 0x21801cbd, 0x00000800, 0x0a682000 },
    { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 },
    { 0x00200001, 0x24a002a9, 0x004501a0, 0x00000000 },
-   { 0x00600001, 0x28200021, 0x008c04a0, 0x00000000 },
-   { 0x00600001, 0x28400021, 0x008c04a0, 0x00000000 },
+   { 0x00600001, 0x28200021, 0x000004a0, 0x00000000 },
+   { 0x00600001, 0x28400021, 0x000004a0, 0x00000000 },
    { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 },
    { 0x00000040, 0x28080c21, 0x00000488, 0x00000008 },
    { 0x00000001, 0x28200021, 0x00000180, 0x00000000 },