// Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
// Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
SDValue LogicOp0 = N0.getOperand(0);
- ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1));
+ ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true);
if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask &&
LogicOp0.getOpcode() == ISD::BITCAST &&
LogicOp0.getOperand(0).getValueType() == VT)
define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {
; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: addps %xmm1, %xmm0
+; CHECK-NEXT: subps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <4 x i32>
%xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 undef, i32 2147483648>
ret <4 x float> %fsub
}
-define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) {
-; CHECK-LABEL: fsub_bitcast_fneg_vec_elts:
+define <4 x float> @fsub_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: fsub_bitcast_fneg_vec_undef_elts:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: subps %xmm1, %xmm0
+; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <4 x float> %y to <4 x i32>
%xor = xor <4 x i32> %bc1, <i32 undef, i32 2147483648, i32 undef, i32 2147483648>