r300-gallium: Move RS block setup to CSO.

diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index e0da9d3..e10d237 100644 (file)
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -1150,6 +1150,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_W_ADDR_MASK                  0x0003f000
 #       define R300_HIRES_DIS                    (0 << 18)
 #       define R300_HIRES_EN                     (1 << 18)
+#       define R300_IT_COUNT(x)                  ((x) << 0)
+#       define R300_IC_COUNT(x)                  ((x) << 7)
+#       define R300_W_COUNT(x)                   ((x) << 12)
 
 #define R300_RS_INST_COUNT                       0x4304
 #       define R300_RS_INST_COUNT_SHIFT          0

diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
index 1913ffc..9968fe0 100644 (file)
--- a/src/gallium/drivers/r300/r300_surface.c
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -63,7 +63,7 @@ static void r300_surface_fill(struct pipe_context* pipe,
     r300_emit_dsa_state(r300, &dsa_clear_state);
     r300_emit_rs_state(r300, &rs_clear_state);
 
-    BEGIN_CS(129 + (caps->is_r500 ? 22 : 14) + (caps->has_tcl ? 4 : 2));
+    BEGIN_CS(128 + (caps->has_tcl ? 2 : 0));
     /* Flush PVS. */
     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
 
@@ -184,42 +184,15 @@ static void r300_surface_fill(struct pipe_context* pipe,
 
     /* XXX */
     OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
-
-    /* RS block setup */
-    if (caps->is_r500) {
-        /* XXX We seem to be in disagreement about how many of these we have
-         * RS:RS_IP_[0-15] [R/W] 32 bits Access: 8/16/32 MMReg:0x4074-0x40b0
-         * Now that's from the docs. I don't care what the mesa driver says */
-        OUT_CS_REG_SEQ(R500_RS_IP_0, 16);
-        for (i = 0; i < 16; i++) {
-            OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-                (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-                (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-                (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
-        }
-        OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
-        OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
-        OUT_CS(0x00000000);
-        OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
-    } else {
-        OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
-        for (i = 0; i < 8; i++) {
-            OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
-                R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
-        }
-        OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
-        OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
-        /* XXX Shouldn't this be 0? */
-        OUT_CS(1);
-        OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
-    }
     END_CS;
 
     /* Fragment shader setup */
     if (caps->is_r500) {
         r500_emit_fragment_shader(r300, &r500_passthrough_fragment_shader);
+        r300_emit_rs_block_state(r300, &r500_rs_block_clear_state);
     } else {
         r300_emit_fragment_shader(r300, &r300_passthrough_fragment_shader);
+        r300_emit_rs_block_state(r300, &r300_rs_block_clear_state);
     }
 
     BEGIN_CS(7 + (caps->has_tcl ? 21 : 2));

diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h
index 807aad3..616d56d 100644 (file)
--- a/src/gallium/drivers/r300/r300_surface.h
+++ b/src/gallium/drivers/r300/r300_surface.h
@@ -69,4 +69,24 @@ const struct r300_rs_state rs_clear_state = {
     .line_stipple_value = 0x0,
 };
 
+const struct r300_rs_block r300_rs_block_clear_state = {
+    .ip[0] = R500_RS_SEL_S(R300_RS_SEL_K0) |
+        R500_RS_SEL_T(R300_RS_SEL_K0) |
+        R500_RS_SEL_R(R300_RS_SEL_K0) |
+        R500_RS_SEL_Q(R300_RS_SEL_K1),
+    .inst[0] = R300_RS_INST_COL_CN_WRITE,
+    .count = R300_IT_COUNT(0) | R300_IC_COUNT(1) | R300_HIRES_EN,
+    .inst_count = 0,
+};
+
+const struct r300_rs_block r500_rs_block_clear_state = {
+    .ip[0] = R500_RS_SEL_S(R500_RS_IP_PTR_K0) |
+        R500_RS_SEL_T(R500_RS_IP_PTR_K0) |
+        R500_RS_SEL_R(R500_RS_IP_PTR_K0) |
+        R500_RS_SEL_Q(R500_RS_IP_PTR_K1),
+    .inst[0] = R500_RS_INST_COL_CN_WRITE,
+    .count = R300_IT_COUNT(0) | R300_IC_COUNT(1) | R300_HIRES_EN,
+    .inst_count = 0,
+};
+
 #endif /* R300_SURFACE_H */