u32 lvds_sync = 0;
int target_clock;
- drm_vblank_pre_modeset(dev, pipe);
-
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
if (encoder->base.crtc != crtc)
continue;
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
if (!ok) {
DRM_ERROR("Couldn't find PLL settings for mode!\n");
- drm_vblank_post_modeset(dev, pipe);
return -EINVAL;
}
intel_update_watermarks(dev);
- drm_vblank_post_modeset(dev, pipe);
-
return ret;
}
u32 lvds_sync = 0;
int target_clock;
- drm_vblank_pre_modeset(dev, pipe);
-
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
if (encoder->base.crtc != crtc)
continue;
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
if (!ok) {
DRM_ERROR("Couldn't find PLL settings for mode!\n");
- drm_vblank_post_modeset(dev, pipe);
return -EINVAL;
}
intel_update_watermarks(dev);
- drm_vblank_post_modeset(dev, pipe);
-
return ret;
}
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
int ret;
+ drm_vblank_pre_modeset(dev, pipe);
+
ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
x, y, old_fb);
+ drm_vblank_post_modeset(dev, pipe);
+
return ret;
}