}
int
-i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+i915_gem_user_to_context_sseu(struct intel_gt *gt,
const struct drm_i915_gem_context_param_sseu *user,
struct intel_sseu *context)
{
- const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *device = >->info.sseu;
+ struct drm_i915_private *i915 = gt->i915;
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
goto out_ce;
}
- ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
+ ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu);
if (ret)
goto out_ce;
struct i915_lut_handle *i915_lut_handle_alloc(void);
void i915_lut_handle_free(struct i915_lut_handle *lut);
-int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+int i915_gem_user_to_context_sseu(struct intel_gt *gt,
const struct drm_i915_gem_context_param_sseu *user,
struct intel_sseu *context);
int inst = 0;
int ret = 0;
- if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg)
+ if (INTEL_GEN(i915) < 9)
return 0;
if (flags & TEST_RESET)
if (hweight32(engine->sseu.slice_mask) < 2)
continue;
+ if (!engine->gt->info.sseu.has_slice_pg)
+ continue;
+
/*
* Gen11 VME friendly power-gated configuration with
* half enabled sub-slices.
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
- *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu);
+ *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
intel_ring_advance(rq, cs);
/* Use the whole device by default */
engine->sseu =
- intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
+ intel_sseu_from_device_info(&engine->gt->info.sseu);
intel_engine_init_workarounds(engine);
intel_engine_init_whitelist(engine);
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
struct drm_printer *p)
{
drm_printf(p, "available engines: %x\n", info->engine_mask);
+
+ intel_sseu_dump(&info->sseu, p);
}
/* Media engine access to SFC per instance */
u8 vdbox_sfc_access;
+
+ /* Slice/subslice/EU info */
+ struct sseu_dev_info sseu;
} info;
};
/* RPCS */
if (engine->class == RENDER_CLASS) {
regs[CTX_R_PWR_CLK_STATE] =
- intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+ intel_sseu_make_rpcs(engine->gt, &ce->sseu);
i915_oa_init_reg_state(ce, engine);
}
static int chv_rps_max_freq(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_gt *gt = rps_to_gt(rps);
u32 val;
val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (RUNTIME_INFO(i915)->sseu.eu_total) {
+ switch (gt->info.sseu.eu_total) {
case 8:
/* (2 * 4) config */
val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT;
static void gen12_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 dss_en;
u16 eu_en = 0;
static void gen11_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 ss_en;
u8 eu_en;
static void gen10_sseu_info_init(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2);
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
static void cherryview_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
u8 subslice_mask = 0;
{
struct drm_i915_private *i915 = gt->i915;
struct intel_device_info *info = mkwrite_device_info(i915);
- struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 fuse2, eu_disable, subslice_mask;
const u8 eu_mask = 0xff;
static void bdw_sseu_info_init(struct intel_gt *gt)
{
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
int s, ss;
u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
static void hsw_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu;
+ struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse1;
u8 subslice_mask = 0;
int s, ss;
gen12_sseu_info_init(gt);
}
-u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
+u32 intel_sseu_make_rpcs(struct intel_gt *gt,
const struct intel_sseu *req_sseu)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ struct drm_i915_private *i915 = gt->i915;
+ const struct sseu_dev_info *sseu = >->info.sseu;
bool subslice_pg = sseu->has_subslice_pg;
u8 slices, subslices;
u32 rpcs = 0;
void intel_sseu_info_init(struct intel_gt *gt);
-u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
+u32 intel_sseu_make_rpcs(struct intel_gt *gt,
const struct intel_sseu *req_sseu);
void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
u8 vals[3] = { 0, 0, 0 };
unsigned int i;
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]))
+ if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
continue;
/*
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1;
+ ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
static void
wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
unsigned int slice, subslice;
u32 l3_en, mcr, mcr_mask;
static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct drm_i915_private *dev_priv = gt->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
}
/* System info */
- blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
+ blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask);
blob->system_info.rcs_enabled = 1;
blob->system_info.bcs_enabled = 1;
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct drm_printer p = drm_seq_file_printer(m);
- intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p);
+ intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p);
return 0;
}
struct sseu_dev_info *sseu)
{
#define SS_MAX 6
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
struct sseu_dev_info *sseu)
{
#define SS_MAX 3
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
int s, ss;
static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
+ const struct intel_gt_info *info = &dev_priv->gt.info;
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
struct drm_file *file_priv)
{
struct drm_i915_private *i915 = to_i915(dev);
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
+ const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
drm_i915_getparam_t *param = data;
int value;
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct intel_engine_coredump *ee)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
+ const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
int slice;
int subslice;
intel_device_info_print_static(&error->device_info, &p);
intel_device_info_print_runtime(&error->runtime_info, &p);
- intel_sseu_print_topology(&error->runtime_info.sseu, &p);
intel_gt_info_print(&error->gt->info, &p);
+ intel_sseu_print_topology(&error->gt->info.sseu, &p);
intel_driver_caps_print(&error->driver_caps, &p);
}
if (!intel_context_pin_if_active(ce))
continue;
- flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
+ flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
err = gen8_modify_context(ce, flex, count);
intel_context_unpin(ce);
if (engine->class != RENDER_CLASS)
continue;
- regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
+ regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
err = gen8_modify_self(ce, regs, num_regs, active);
if (err)
get_default_sseu_config(struct intel_sseu *out_sseu,
struct intel_engine_cs *engine)
{
- const struct sseu_dev_info *devinfo_sseu =
- &RUNTIME_INFO(engine->i915)->sseu;
+ const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
*out_sseu = intel_sseu_from_device_info(devinfo_sseu);
drm_sseu->engine.engine_instance != engine->uabi_instance)
return -EINVAL;
- return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu);
+ return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
}
/**
static int query_topology_info(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
int ret;
#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"
-#include "gt/intel_sseu.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
void intel_device_info_print_runtime(const struct intel_runtime_info *info,
struct drm_printer *p)
{
- intel_sseu_dump(&info->sseu, p);
-
drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
drm_printf(p, "CS timestamp frequency: %u Hz\n",
info->cs_timestamp_frequency_hz);
u8 num_sprites[I915_MAX_PIPES];
u8 num_scalers[I915_MAX_PIPES];
- /* Slice/subslice/EU info */
- struct sseu_dev_info sseu;
-
u32 rawclk_freq;
u32 cs_timestamp_frequency_hz;