Merge remote branch 'anholt/drm-intel-next' into drm-linus

Pull more Intel changes in, especially one to init the GTT properly

diff --combined drivers/char/agp/intel-agp.c
index 3767855,33b4853..30c36ac
--- 1/drivers/char/agp/intel-agp.c
--- 2/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@@ -62,7 -62,6 +62,7 @@@
  #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG         0x0042
  #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB         0x0044
  #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB        0x0062
 +#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a
  #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG         0x0046
  
  /* cover 915 and 945 variants */
@@@ -97,8 -96,7 +97,8 @@@
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
 -              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB)
 +              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
 +              agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB)
  
  extern int agp_memory_reserved;
  
@@@ -178,6 -176,7 +178,7 @@@ static struct _intel_private 
         * popup and for the GTT.
         */
        int gtt_entries;                        /* i830+ */
+       int gtt_total_size;
        union {
                void __iomem *i9xx_flush_page;
                void *i8xx_flush_page;
@@@ -1153,7 -1152,7 +1154,7 @@@ static int intel_i915_configure(void
        readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
  
        if (agp_bridge->driver->needs_scratch_page) {
-               for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
+               for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
                        writel(agp_bridge->scratch_page, intel_private.gtt+i);
                }
                readl(intel_private.gtt+i-1);   /* PCI Posting. */
@@@ -1163,6 -1162,12 +1164,6 @@@
  
        intel_i9xx_setup_flush();
  
 -#ifdef USE_PCI_DMA_API 
 -      if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
 -              dev_err(&intel_private.pcidev->dev,
 -                      "set gfx device dma mask 36bit failed!\n");
 -#endif
 -
        return 0;
  }
  
@@@ -1308,6 -1313,8 +1309,8 @@@ static int intel_i915_create_gatt_table
        if (!intel_private.gtt)
                return -ENOMEM;
  
+       intel_private.gtt_total_size = gtt_map_size / 4;
+ 
        temp &= 0xfff80000;
  
        intel_private.registers = ioremap(temp, 128 * 4096);
@@@ -1360,7 -1367,6 +1363,7 @@@ static void intel_i965_get_gtt_range(in
        case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB:
        case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB:
        case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB:
 +      case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB:
                *gtt_offset = *gtt_size = MB(2);
                break;
        default:
@@@ -1395,6 -1401,8 +1398,8 @@@ static int intel_i965_create_gatt_table
        if (!intel_private.gtt)
                return -ENOMEM;
  
+       intel_private.gtt_total_size = gtt_size / 4;
+ 
        intel_private.registers = ioremap(temp, 128 * 4096);
        if (!intel_private.registers) {
                iounmap(intel_private.gtt);
@@@ -2362,8 -2370,6 +2367,8 @@@ static const struct intel_driver_descri
            "Ironlake/M", NULL, &intel_i965_driver },
        { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
            "Ironlake/MA", NULL, &intel_i965_driver },
 +      { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0,
 +          "Ironlake/MC2", NULL, &intel_i965_driver },
        { 0, 0, 0, NULL, NULL, NULL }
  };
  
@@@ -2455,11 -2461,6 +2460,11 @@@ static int __devinit agp_intel_probe(st
                                &bridge->mode);
        }
  
 +      if (bridge->driver->mask_memory == intel_i965_mask_memory)
 +              if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
 +                      dev_err(&intel_private.pcidev->dev,
 +                              "set gfx device dma mask 36bit failed!\n");
 +
        pci_set_drvdata(pdev, bridge);
        return agp_add_bridge(bridge);
  }
@@@ -2565,7 -2566,6 +2570,7 @@@ static struct pci_device_id agp_intel_p
        ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
        ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
        ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
 +      ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
        { }
  };
  

diff --combined drivers/gpu/drm/i915/i915_drv.h
index df5b943,1d61710..fbecac7
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -305,7 -305,6 +305,7 @@@ typedef struct drm_i915_private 
        u32 saveVBLANK_A;
        u32 saveVSYNC_A;
        u32 saveBCLRPAT_A;
 +      u32 saveTRANSACONF;
        u32 saveTRANS_HTOTAL_A;
        u32 saveTRANS_HBLANK_A;
        u32 saveTRANS_HSYNC_A;
@@@ -336,7 -335,6 +336,7 @@@
        u32 saveVBLANK_B;
        u32 saveVSYNC_B;
        u32 saveBCLRPAT_B;
 +      u32 saveTRANSBCONF;
        u32 saveTRANS_HTOTAL_B;
        u32 saveTRANS_HBLANK_B;
        u32 saveTRANS_HSYNC_B;
@@@ -383,8 -381,6 +383,6 @@@
        u32 saveFDI_RXA_IMR;
        u32 saveFDI_RXB_IMR;
        u32 saveCACHE_MODE_0;
-       u32 saveD_STATE;
-       u32 saveDSPCLK_GATE_D;
        u32 saveMI_ARB_STATE;
        u32 saveSWF0[16];
        u32 saveSWF1[16];
@@@ -425,16 -421,6 +423,16 @@@
        u32 savePFB_WIN_SZ;
        u32 savePFA_WIN_POS;
        u32 savePFB_WIN_POS;
 +      u32 savePCH_DREF_CONTROL;
 +      u32 saveDISP_ARB_CTL;
 +      u32 savePIPEA_DATA_M1;
 +      u32 savePIPEA_DATA_N1;
 +      u32 savePIPEA_LINK_M1;
 +      u32 savePIPEA_LINK_N1;
 +      u32 savePIPEB_DATA_M1;
 +      u32 savePIPEB_DATA_N1;
 +      u32 savePIPEB_LINK_M1;
 +      u32 savePIPEB_LINK_N1;
  
        struct {
                struct drm_mm gtt_space;

diff --combined drivers/gpu/drm/i915/i915_irq.c
index ae17c4b,a1345d7..85f4c5d
--- 1/drivers/gpu/drm/i915/i915_irq.c
--- 2/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@@ -273,15 -273,10 +273,15 @@@ irqreturn_t ironlake_irq_handler(struc
  {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        int ret = IRQ_NONE;
 -      u32 de_iir, gt_iir, pch_iir;
 +      u32 de_iir, gt_iir, de_ier, pch_iir;
        u32 new_de_iir, new_gt_iir, new_pch_iir;
        struct drm_i915_master_private *master_priv;
  
 +      /* disable master interrupt before clearing iir  */
 +      de_ier = I915_READ(DEIER);
 +      I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 +      (void)I915_READ(DEIER);
 +
        de_iir = I915_READ(DEIIR);
        gt_iir = I915_READ(GTIIR);
        pch_iir = I915_READ(SDEIIR);
@@@ -329,9 -324,6 +329,9 @@@
                pch_iir = new_pch_iir;
        }
  
 +      I915_WRITE(DEIER, de_ier);
 +      (void)I915_READ(DEIER);
 +
        return ret;
  }
  
@@@ -546,7 -538,6 +546,6 @@@ static void i915_handle_error(struct dr
                /*
                 * Wakeup waiting processes so they don't hang
                 */
-               printk("i915: Waking up sleeping processes\n");
                DRM_WAKEUP(&dev_priv->irq_queue);
        }
  

diff --combined drivers/gpu/drm/i915/i915_suspend.c
index ab35e81,00f6d97..d5ebb00
--- 1/drivers/gpu/drm/i915/i915_suspend.c
--- 2/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@@ -239,11 -239,6 +239,11 @@@ static void i915_save_modeset_reg(struc
        if (drm_core_check_feature(dev, DRIVER_MODESET))
                return;
  
 +      if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
 +              dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
 +      }
 +
        /* Pipe & plane A info */
        dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
        dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@@ -268,11 -263,6 +268,11 @@@
                dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
  
        if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
 +              dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
 +              dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
 +              dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
 +
                dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
                dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
  
@@@ -280,7 -270,6 +280,7 @@@
                dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
                dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
  
 +              dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
                dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
                dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
                dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
@@@ -325,11 -314,6 +325,11 @@@
                dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
  
        if (IS_IRONLAKE(dev)) {
 +              dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
 +              dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
 +              dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
 +              dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
 +
                dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
                dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
  
@@@ -337,7 -321,6 +337,7 @@@
                dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
                dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
  
 +              dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
                dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
                dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
                dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
@@@ -385,11 -368,6 +385,11 @@@ static void i915_restore_modeset_reg(st
                fpb1_reg = FPB1;
        }
  
 +      if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
 +              I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
 +      }
 +
        /* Pipe & plane A info */
        /* Prime the clock */
        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@@ -417,11 -395,6 +417,11 @@@
                I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
  
        if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
 +              I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
 +              I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
 +              I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 +
                I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
                I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
  
@@@ -429,7 -402,6 +429,7 @@@
                I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
                I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
  
 +              I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
                I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
                I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
                I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
@@@ -467,7 -439,7 +467,7 @@@
        /* Actually enable it */
        I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
        DRM_UDELAY(150);
 -      if (IS_I965G(dev))
 +      if (IS_I965G(dev) && !IS_IRONLAKE(dev))
                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
        DRM_UDELAY(150);
  
@@@ -482,11 -454,6 +482,11 @@@
                I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
  
        if (IS_IRONLAKE(dev)) {
 +              I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
 +              I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
 +              I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
 +              I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 +
                I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
                I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
  
@@@ -494,7 -461,6 +494,7 @@@
                I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
                I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
  
 +              I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
                I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
                I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
                I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
@@@ -756,10 -722,6 +756,6 @@@ int i915_save_state(struct drm_device *
                dev_priv->saveIMR = I915_READ(IMR);
        }
  
-       /* Clock gating state */
-       dev_priv->saveD_STATE = I915_READ(D_STATE);
-       dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
- 
        /* Cache mode state */
        dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
  
@@@ -834,8 -796,7 +830,7 @@@ int i915_restore_state(struct drm_devic
        }
  
        /* Clock gating state */
-       I915_WRITE (D_STATE, dev_priv->saveD_STATE);
-       I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
+       intel_init_clock_gating(dev);
  
        /* Cache mode state */
        I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);

diff --combined drivers/gpu/drm/i915/intel_display.c
index 5146b80,279dc96..52cd9b0
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -32,7 -32,7 +32,7 @@@
  #include "intel_drv.h"
  #include "i915_drm.h"
  #include "i915_drv.h"
 -#include "intel_dp.h"
 +#include "drm_dp_helper.h"
  
  #include "drm_crtc_helper.h"
  
@@@ -4584,28 -4584,33 +4584,33 @@@ void intel_init_clock_gating(struct drm
                struct drm_i915_gem_object *obj_priv;
                int ret;
  
-               pwrctx = drm_gem_object_alloc(dev, 4096);
-               if (!pwrctx) {
-                       DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
-                       goto out;
-               }
+               if (dev_priv->pwrctx) {
+                       obj_priv = dev_priv->pwrctx->driver_private;
+               } else {
+                       pwrctx = drm_gem_object_alloc(dev, 4096);
+                       if (!pwrctx) {
+                               DRM_DEBUG("failed to alloc power context, "
+                                         "RC6 disabled\n");
+                               goto out;
+                       }
  
-               ret = i915_gem_object_pin(pwrctx, 4096);
-               if (ret) {
-                       DRM_ERROR("failed to pin power context: %d\n", ret);
-                       drm_gem_object_unreference(pwrctx);
-                       goto out;
-               }
+                       ret = i915_gem_object_pin(pwrctx, 4096);
+                       if (ret) {
+                               DRM_ERROR("failed to pin power context: %d\n",
+                                         ret);
+                               drm_gem_object_unreference(pwrctx);
+                               goto out;
+                       }
  
-               i915_gem_object_set_to_gtt_domain(pwrctx, 1);
+                       i915_gem_object_set_to_gtt_domain(pwrctx, 1);
  
-               obj_priv = pwrctx->driver_private;
+                       dev_priv->pwrctx = pwrctx;
+                       obj_priv = pwrctx->driver_private;
+               }
  
                I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
                I915_WRITE(MCHBAR_RENDER_STANDBY,
                           I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
- 
-               dev_priv->pwrctx = pwrctx;
        }
  
  out: